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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李世光 | |
dc.contributor.author | Po-Cheng Lai | en |
dc.contributor.author | 賴柏誠 | zh_TW |
dc.date.accessioned | 2021-06-08T04:17:29Z | - |
dc.date.copyright | 2010-08-03 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-07-29 | |
dc.identifier.citation | [1] O. Heil, British Patent No.439457, 1935.
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Ferrari , 'Al2O3 as gate dielectric for organic transistors: Charge transport phenomena in poly-(3-hexylthiophene) based devices,' Organic Electronics, pp.198–208, 2008 [14] J. H. Lee, K. Koh, N. I. Lee, M. H. Cho, Y. K. Kim, J. S. Jeon, K. H. Cho, H. S. Shin, M. H. Kim, K. Fugihara, H. K. Kang and J. T. Moon, “Effect of Polysilicon Gate on the Flatband Voltage Shift and Mobility Degradation for ALD-Al2O3 Gate Dielectric,” IEDM Tech. Dig., p. 645-648, 2000. [15] H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, “High-k Gate Dielectrics with Ultra-low Leakage Current Based on Praseodyminum Oxide,” IEDM Tech. Dig., p. 653-656, 2000. [16] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical Characteristics of Highly Reliable Ultra-thin Hafnium Oxide Gate Dielectric,” IEEE Electron Device Lett., Vol. 21, pp. 181-183, Apr. 2000. [17] F. Y. Yen, C. L. Hung, Y. T. Hou, P. F. Hsu, V. S. Chang, P. S. Lim, L. G. Yao, J. C. Jiang, H. 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Ting, Y. H. Shih, and J. G. Hwu, “Ultralow Leakage Characteristics of Ultrathin Gate Oxides (3 nm) Prepared by Anodization Followed by High-Temperature Annealing,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 179–181, January 2002. [22] S. lijima and T. Ichihashi, “Single-shell carbon nanotubes of 1-nm diameter,” Nature, Vol. 363, 17 June 1993. [23] R. Martel, V. Derycke, J. Appenzeller, S. Wind and Ph. Avouris, ”Carbon Nanotube Field-Effect Transistors and Logic Circuits,” 39th annual Design Automation Conference, 2002. [24] E.S. Snow, J.P. Novak, P.M. Campbell and D. Park, “Random networks of carbon nanotubes as an electronic material,” Applied Physics Letters, Volume 82, Number 13, 31 March 2003. [25] E. S. Snow, P. M. Campbell, M. G. Ancona,and J. P. Novak, “High-mobility carbon-nanotube thin-film transistors on a polymeric substrate,” Applied Physics Letters, 86, 2005. [26] K. Bradley, J. C. P. Gabriel, and G. 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Avouris, “Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown,” 27 April, Vol. 292, Science, 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22423 | - |
dc.description.abstract | 過去薄膜電晶體的製程複雜、手續繁瑣,常常需要在高潔淨度之無塵室中製作,導致製作成本十分的高昂。本論文以設計開發出可以在室溫下進行製作為目標,並朝大面積、可撓曲的方向前進。
首先,先利用鍍膜技術,從高介電值之金屬鋁、鈦、鉭等金屬做為電晶體的閘極,再藉由簡易的電化學、酸鹼反應、氧化還原、電漿反應等常溫下可以操作的方式,來使上述金屬產生不導電的氧化物,進而達到在閘極上直接產生高介電係數閘極介電層。接著,再以奈米碳管和溶膠凝膠法之氧化鋅分別作為薄膜電晶體之主動層,同時也達成低溫製程的目的。 完成上述步驟後,薄膜電晶體元件就大功告成。再以探針台量測所製作出的薄膜電晶體之載子遷移率、閘極電壓對汲極電流的關係和元件開關比等元件之參數,來驗證所製作之元件可達應用程度。 未來可嘗試將原本矽晶圓的基板改以塑膠基板來代替,並將尋找透明之電極材料取代金屬電極,來重複上述之薄膜電晶體之製作過程,以祈能提升整體薄膜電晶體之透明度和可撓曲度,使元件能更臻完美。 | zh_TW |
dc.description.abstract | A newly developed process for making high-K dielectric thin film transistors is presented. Starting from a Silicon substrate, high-K materials such as Aluminum, Titanium and Tantalum were coated to form the metal gate. As these three chosen materials can be easily oxidized, the gate insulator on top of the metal gate can thus be fabricated by oxidization, electroplating, wet chemical process, high-temperature furnace oxidization, or even oxygen plasma in room temperate. This process naturally leads to small gate thickness. Furthermore, Aluminum oxides, Titanium oxides and Tantalum oxides have high enough dielectric constant, band gap and have good contact to the original metal gate when compared to many other materials. When compared to previous processes based on using chemical vapor deposition (CVD) to deposit SiO2, SiNX or some low-K materials to make the gate insulator, the above-mentioned process fabricated the gate and the gate insulator (Aluminum oxide, Titanium oxide and Tantalum oxide) thin film without the need to deposit the insulator layer separately. It is to be noted that this process contains only low temperature processes after the metal gate is deposited, which means that this process can be used for flexible electronics once the substrate is changed from silicon to flexible substrate. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:17:29Z (GMT). No. of bitstreams: 1 ntu-99-R97543004-1.pdf: 12811239 bytes, checksum: 04df9fe918483db37e60a5fb946e549b (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | 論文口試委員審定書
致謝 中文摘要……………………………………………………………i 英文摘要………………………………………………………………ii 目錄……………………………………………………………………iii 圖目錄 …………………………………………………………………vi 表目錄 …………………………………………………………………xiv 第一章 緒論…………………………………………………………1 1.1 研究動機………………………………………………………1 1.2 文獻回顧 ……………………………………………………2 1.2.1 薄膜電晶體……………………………………………2 1.2.2 奈米碳管(Carbon nanotube,CNT)……………………………5 1.2.3 溶膠凝膠法(sol-gel)氧化鋅(ZnO)……………………………9 1.3 論文架構…………………………………………………………10 第二章 薄膜電晶體之理論與架構………………………………….11 2.1 薄膜電晶體架構…………………………………………………11 2.2 薄膜電晶體操作原理……………………………………………13 2.3 高介電值閘極介電層……………………………………………18 2.4 製作閘極氧化層之方法…………………………………………21 2.4.1 酸鹼氧化還原法………………………………………………21 2.4.2 電化學氧化還原法……………………………………………22 2.4.3 電漿氧化法……………………………………………………24 2.4.4 高溫氧化法……………………………………………………25 2.5 閘極介電層厚度之計算與量測…………………………………25 2.6 主動層……………………………………………………………30 2.6.1 奈米碳管………………………………………………………31 2.6.2 氧化鋅…………………………………………………………32 2.7 X光繞射儀 (X-Ray Diffraction)………………………………33 2.8 原子力顯微鏡(Atomic Force Microscope)……………………36 第三章 研究方法、實驗架構與步驟…………………………………39 3.1 實驗架構與製作流程……………………………………………39 3.2 晶圓之規格與清洗晶圓…………………………………………40 3.3 閘極製作流程……………………………………………………42 3.4 高介電值閘極介電層之製作……………………………………43 3.4.1 酸鹼氧化還原法………………………………………………43 3.4.2 電化學氧化還原法……………………………………………43 3.4.3 電漿氧化法……………………………………………………46 3.4.4 高溫氧化法……………………………………………………46 3.5 X光粉末繞射儀量測……………………………………………46 3.6 光學顯微鏡、原子力顯微鏡與電子顯微鏡量測………………47 3.7 閘極之電容值量測………………………………………………47 3.8 源極與汲極之製作………………………………………………48 3.9 主動層之製作與封裝……………………………………………50 3.9.1 奈米碳管………………………………………………………50 3.9.2 溶膠凝膠法氧化鋅……………………………………………52 3.10 電流-電壓曲線分析…………………………………………52 第四章 結果與討論……………………………………………………55 4.1 X光繞射儀量測結果……………………………………………55 4.2 原子力顯微鏡量測結果………………………………………60 4.2.1 矽晶圓表面…………………………………………………60 4.2.2 鍍金屬後表面………………………………………………62 4.2.3 經化學處理後之表面………………………………………65 4.2.4 經電漿處理後之表面………………………………………80 4.2.5 經電化學處理後之表面……………………………………94 4.2.6 經高溫處理後之表面………………………………………114 4.3 電容測試結果……………………………………………………120 4.3.1 化學處理……………………………………………………123 4.3.2 電漿處理……………………………………………………124 4.3.3 電化學處理…………………………………………………125 4.3.4 高溫處理……………………………………………………127 4.4 主動層量測結果…………………………………………………128 4.4.1 奈米碳管………………………………………………………128 4.4.2 溶膠凝膠法氧化鋅……………………………………………135 4.5 電流-電壓曲線分析……………………………………………140 第五章 結論與未來展望……………………………………………195 5.1 結論……………………………………………………………195 5.2 未來展望………………………………………………………196 參考文獻………………………………………………………………197 | |
dc.language.iso | zh-TW | |
dc.title | 高介電值閘極介電層低溫製程薄膜電晶體的研究與開發 | zh_TW |
dc.title | Low-temperature Fabrication Process for High-K Gate Dielectrics Thin Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 林世明 | |
dc.contributor.oralexamcommittee | 吳文中,林致廷 | |
dc.subject.keyword | 高介電值,金屬閘極,低溫製程,奈米碳管,氧化鋅,薄膜電晶體, | zh_TW |
dc.subject.keyword | High-K,High-K dielectric,metal gate,low temperature fabrication,thin film transistor, | en |
dc.relation.page | 202 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2010-07-29 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 應用力學研究所 | zh_TW |
顯示於系所單位: | 應用力學研究所 |
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