請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22409完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 高振宏 | |
| dc.contributor.author | Ting-Li Yang | en |
| dc.contributor.author | 楊挺立 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:17:10Z | - |
| dc.date.copyright | 2010-08-09 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-07-29 | |
| dc.identifier.citation | 參考文獻
[1]. E. M. Davis, W. E. Harding, R. S. Schwartz and J. J. Corning, IBM J. Res. Develop, 8, pp.102, (1964) [2]. D. P. Seraphim, R. C. Lasky, and C-Y. Li, “ Principle of Electronic Package ”, McGraw-Hill, New York, (1993). [3]. J. H. Lau, “ Flip Chip Technologies ”, McGraw-Hill, New York, (1996). [4]. J. H. Lau, “ Low cost flip chip technologies : for DCA, WLCSP, and PBGA assemblies ”, McGraw-Hill, New York, (2002). [5]. K. N. Tu, Journal of Applied Physics. Appl. Phys. 94, 5451 (2003). [6]. S. H. Chiu, T. L. Shao, C. Chen, D. J. Yao, and C.Y. Hsu, Applied Physics Letters 88 (2006). [7]. C. Y. Chang, S. M. Sze, ULSI Technology, the McGRAW-HILL, pp. 663 (1996). [8]. K. N. Tu, Phys. Rev. B 45, 1409 (1992). [9]. Tu K N, Gusak A M, Li M. Physics and materials challenges for lead-free solders, Journal of Applied Physics, 2003, 93(3):1335 - 1353. [10]. E. C. C. Yeh and K. N. Tu, Journal of Applied Physics 88 (2000) 5680 [11]. Ye H, Basaran C, Hopkins D. Applied Physics Letters, 2003, 82 (7) :1045 – 1047. [12]. H. Gan, and K. N. Tu, Journal of Applied Physics, Vol. 97, 2005, pp. 063514-1~063514-10. [13]. Y.-S. Lai, K. M. Chen. C. L. Kao et al, Microelectronics Reliability 47 (2007) 1273–1279 [14]. T. Y. Lee, K. N. Tu, S. M. Kuo, and D. R. Frear, Journal of Applied Physics, Vol. 89 (6), pp.3189-3194, (2001) [15]. Dae-Gon Kim, Won-Chul Moon, Seung-Boo Jung, Microelectronic Engineering, 2006, 83 (11/12) : 2391-2395 [16]. K. Nakagawa, S. Baba, M. Watanabe, H. Matsushima, K. Harada, E. Hayashi, Q. Wu, A. Maeda, M. Nakanishi, and N. Ueda, Proceedings of 51th Electronic Components and Technology Conference, (2001) [17]. Seung-Hyun Chae, Xuefeng Zhang, Huang-Lin Chao, Kuan-Hsun Lu and Paul S. Ho, 2006 Electronic Components and Technology Conference. [18]. F. Ren, J.W. Nah, H. Gan, J.O. Suh, K.N. Tu, B. Xiong, L. Xu, and J. Pang, in Materials, Technology and Reliability of Advanced Interconnects—2005, edited by P.R. Besser, A. J. McKerrow, F. Iacopi, C.P. Wong, and J. Vlassak ( Mater. Res. Soc. Symp. Proc. 863, Warrendale, PA, 2005), B10.2. [19]. Y. C. Hsu, T. L. Shao, C. J. Yang, and C. Chen, Journal of Electronic Materials, Vol. 32 (11), pp.1222-1227, (2003). [20]. X. F. Zhang, J. D. Guo, and J. K. Shang, Scripta Materialia, 2007, 57(6) : 513-516. [21]. Chih-ming Chen, Chih-chieh Huang, Journal of Alloys and Compounds 461 (2008) 235–241 [22]. X U Guang-chen, HE Hong-wen, NIE Jing-kai, GUO Fu, Electronic Components and Materials, Vol.27, No.11, Nov.2008 [23]. E. C. C. Yeh, W. J. Choi, K. N. Tu, P. Elenius, and H. Balkan, Applied Physics Letters 88 (2002) 580. [24]. Y. C. Hu, Y. H. Lin, C. R. Kao, and K. N. Tu, Journal of Materials Research 18 (2003) 2544. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22409 | - |
| dc.description.abstract | 隨著電子元件的構裝密度不斷提高以及不斷朝向高功能、微型化發展,覆晶封裝(Flip-Chip package)技術已成為半導體工業中高階電子元件,如CPU、GPU ( 繪圖晶片 )的主流封裝技術。近年來覆晶銲點的直徑以及間距 ( Pitch ) 不斷縮小,導致通過覆晶銲點的電流密度持續攀升,而高電流密度所引發之電遷移現象將使得作為晶片與基板連接線路的銲點成為相對脆弱的接點,進而影響覆晶元件的可靠度。因此,電遷移效應已成為高階電子元件可靠度的重要研究內容之一。
電遷移效應中「電流密度」與「溫度」兩大因素,對覆晶封裝的失效機制而言一直是相當重要並難以分開討論。許多研究此兩大因素的電遷移文獻中,大多以固定電流密度,改變不同環境溫度來進行研究,鮮少能在固定晶片溫度下,進行不同電流密度間的探討。本研究透過良好的溫度控制系統,以強制對流的方式解決了因高電流密度所造成的大量焦耳熱並成功將晶片端溫度予以控制,試圖將「熱遷移」效應從高電流密度加速測試中降至最低。本研究所使用之覆晶銲點結構為Al導線/Ti(1K)/Cu(2K)/Cu(8μm)/Sn2.6Ag/Cu/Cu導線,所施加之電流密度分別為3.5×104A/cm2、4.5×104A/cm2、5.5×104A/cm2,並將晶片端溫度控制於50℃。針對加裝與未加裝溫度控制系統的覆晶元件實驗結果比較發現,在恆溫控制下不僅能延長覆晶銲點之壽命 ( 超過1500小時 ),更發現與過去「高溫」通電加速測試中截然不同的界面形貌,本論文也試圖對此一特殊界面形貌的分佈、形狀與形成原因加以探討、解釋。 | zh_TW |
| dc.description.abstract | With the requirement for decreasing packaging size and increasing quantity for interconnect efficient, flip chip package has become a predominant technology for CPU and GPU…The miniaturization of bump pitch always accompany the rise of interconnect current density, and it will made the solder joint of the device a weakly spot, which makes the subsequent electromigration phenomenon cannot be ignored.
Current density and temperature are two key effects in flip chip electromigration study, and it is very important and hard to separate to discuss. In the past few years, many studies were carried out to investigate the reliability of solder joints under the condition of the same current density but varied ambient temperature. However, there were few studies can successfully investigate the condition of fixed chip temperature but varied current density. In this research, a temperature control system, employing forced fluid convection, was adopted to separate thermomigration and electromigration effect in flip chip solder joints. With this temperature control system, the die temperature can be precisely fixed at 50 ℃ under different current density ( 3.5×104 A/cm2、4.5×104 A/cm2、5.5×104 A/cm2). The configuration of flip chip solder joint in this research is Ti(1K)/Cu(2K)/Cu(8μm)/Sn2.6Ag/Cu. And the experimental results showed that temperature control system could prolong the life of solder joints even under extra high current density ( over 1860h ). Results also indicate an unique “ sawtooth-type ” Cu UBM morphology was retained at the cathode/chip or substrate side during high current stressing compared with the past accelerated tests. This thesis will discuss the morphology and shape of this unique “ sawtooth-type ” Cu UBM morphology, and give some possible reasons for the formation of this unique morphology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:17:10Z (GMT). No. of bitstreams: 1 ntu-99-R97527012-1.pdf: 16804845 bytes, checksum: 72798bad0d6549eaa9a9bc0797b78dcd (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 目錄
中文摘要.........................................................................................................................II Abstract..........................................................................................................................III 目錄...............................................................................................................................IV 圖目錄..........................................................................................................................VII 表目錄....................................................................................................................... XIV 第一章 緒論................................................................................................................1 1.1 研究背景.......................................................................................................1 1.2 研究動機.......................................................................................................4 第二章 文獻回顧........................................................................................................6 2.1 電遷移原理...................................................................................................6 2.1.1 電遷移現象............................................................................................6 2.1.2 電遷移擴散通量...................................................................................7 2.2 覆晶封裝中銲點的電遷移特性...................................................................8 2.2.1 電流聚集效應........................................................................................8 2.2.2 焦耳熱效應..........................................................................................10 2.2.3 介金屬化合物 ( IMC ) 的極化效應.................................................12 2.3 電遷移在不同銲料組成下的現象........................................................13 2.3.1 含鉛銲料..............................................................................................13 2.3.2 無鉛銲料..............................................................................................16 2.4 覆晶封裝中銲點的電遷移效應..... ...........................................................20 2.4.1 Void formation and propagation..........................................................20 2.4.2 UBM consumption...............................................................................20 第三章 實驗方法與步驟..........................................................................................24 3.1 覆晶封裝試片結構.....................................................................................24 3.2 實驗裝置.....................................................................................................25 3.3 試片通電.....................................................................................................27 3.4 金相處理.....................................................................................................27 3.5 儀器分析.....................................................................................................28 3.6 實驗條件.....................................................................................................28 第四章 實驗結果.....................................................................................................30 4.1 未加裝溫度控制裝置的通電結果.............................................................30 4.2 加裝溫度控制裝置的通電結果.................................................................34 4.2.1 通電覆晶試片的溫度量測.................................................................34 4.2.2 銲點A,3.5×104A/cm2,晶片端溫度 : 50℃,1500小時停止實驗.....35 4.2.3 銲點B,3.5×104A/cm2,晶片端溫度 : 50℃,1500小時停止實驗.....35 4.2.4 銲點A,4.5×104A/cm2,晶片端溫度 : 50℃,1500小時停止實驗.....38 4.2.5 銲點B,4.5×104A/cm2,晶片端溫度 : 50℃,1500小時停止實驗.....38 4.2.6 銲點A,5.5×104A/cm2,晶片端溫度 : 50℃,130小時失效........43 4.2.7 銲點B,5.5×104A/cm2,晶片端溫度 : 50℃,130小時失效........43 第五章 討論..............................................................................................................47 5.1 「Sawtooth morphology」鋸齒狀形貌的分佈、形狀、形成原因..........47 5.1.1 銲點A,4.5×104A/cm2,晶片端溫度 : 50℃,1500小時停止實驗.....47 5.1.2 銲點A,4.5×104A/cm2,晶片端溫度 : 50℃,1000小時停止實驗.....48 5.1.3 「Sawtooth morphology」 鋸齒狀形貌形狀與形成原因....................48 5.2 銲點B於chip端出現孔洞的原因............................................................60 5.2.1 chip端孔洞的確認..............................................................................60 5.2.2 銲點B,4.5×104A/cm2,晶片端溫度 : 50℃,1000小時停止實驗.....60 5.2.3 銲點B,4.5×104A/cm2,晶片端溫度 : 50℃,1000小時孔洞的產 生原因..................................................................................................61 第六章 結論..............................................................................................................66 參考文獻........................................................................................................................67 | |
| dc.language.iso | zh-TW | |
| dc.subject | 金屬間化合物 | zh_TW |
| dc.subject | 覆晶封裝 | zh_TW |
| dc.subject | 電遷移 | zh_TW |
| dc.subject | 熱遷移 | zh_TW |
| dc.subject | Flip Chip Electromigration | en |
| dc.subject | Intermetallic Compound | en |
| dc.subject | Thermomigration | en |
| dc.title | 局部溫度控制下電遷移對覆晶封裝中UBM消耗及其失效機制研究 | zh_TW |
| dc.title | Study of UBM Consumption in Flip Chip Solder Joints with Local Temperature Control | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳智,陳志銘,吳子嘉,顏怡文 | |
| dc.subject.keyword | 覆晶封裝,電遷移,熱遷移,金屬間化合物, | zh_TW |
| dc.subject.keyword | Flip Chip Electromigration,Thermomigration,Intermetallic Compound, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2010-07-30 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
| 顯示於系所單位: | 材料科學與工程學系 | |
文件中的檔案:
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-99-1.pdf 未授權公開取用 | 16.41 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。
