請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22217完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥 | |
| dc.contributor.author | Jui Wang | en |
| dc.contributor.author | 王睿 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:13:56Z | - |
| dc.date.copyright | 2010-08-19 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-15 | |
| dc.identifier.citation | [1] Chris Spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 2nd ed., New York: Springer-Verlag, 2008
[2] Universal Serial Bus 3.0 Specification, Rev.1.0, 2008 [3] SystemVerilog 3.1a Language Reference Manual, 2004 [4] Paul Hoxey, Clayton McDonald, and David Guinther, An introduction to symbolic simulation, EE Times, http://www.eetimes.com/ [5] J. Bergeron, H. Foster, A. Piziali, R. S. Mitra, C. Ahlschlager, and D. Stein, “Building A Verification Test Plan:Trading Brute Force For Finesse”, in Proceedings of the 43rd annual Design Automation Conference, San Francisco, CA, USA, 2006, pp. 805 – 806 [6] Noah Bamford, Rekha K. Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, and Edgar Jimenez, “Challenges in System on Chip Verification”, in Proceedings of the Seventh International Workshop on Microprocessor Test and Verification, 2006, pp. 52–60 [7] Francine Bacchini, Alan J. Hu, “Verification Coverage: When is Enough, Enough?”, Design Automation Conference, pp. 744-745, 2007. [8] A. Molina and O. Cadenas, “Functional Verification: Approaches And Challenges”, Latin American Applied Research, 37:65-69, 2007 [9] “Functional Verification of Digital Circuits using a Software System”, Proceedings of the 2008 IEEE International Conference on Automation, Quality and Testing, Robotics - Volume 01, pp.152-157, 2008 [10] Chien-Chih Yu, “System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express,” Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2004 [11] Ting-Chun Huang, “A Functional Verification Environment for Advanced Switching Architecture,” Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2004. [12] Chih-Neng Chung, “Implementations of Bus Functional Models for the PCI Express System,” Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2004. [13] Kuan-Lin Chen, “Verification Environment of High-speed Serial Bus System”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2006. [14] Che-Yang Shen, “System Level Verification for Serial Advanced Technology Attachment Models”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2006. [15] Tze-Lin Wu, “Bus Function Models for the Consumer Electronics – Advanced Technology Attachment System”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2006. [16] Yang-Song Wang, “Verification Environment for I/O Virtualization”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2008. [17] Huan-Wen Chen, “Hybrid Functional Verification Methodology for Alpha Processor Using RTL Symbolic Simulation”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2008. [18] Hung-Po Wang, “Verification and Implementation of Bus Functional Models for USB System”, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22217 | - |
| dc.description.abstract | 今日積體電路設計的複雜度快速成長，使原本已經是電路設計流程中瓶頸的功能性驗證變得更加耗時，加上各種技術日新月異，新產品上市有時程上的限制，要在有限的時間內完成設計、驗證到下線生產的流程，對業界來說是不容小覷的議題。為了解決這個問題，一個有效率且完整的驗證環境占有非常重要的地位。
本論文設計並實作一個階層式，基於物件導向語言SystemVerilog的驗證環境，利用SystemVerilog中的Constrained-Random Stimulus Generation 功能，在有限的集合中隨機產生測試向量，以提高找到電路錯誤的機率，使驗證更加完整可靠；利用其物件導向的特性，提高程式碼重複使用率，不僅加速驗證程序、也簡化測試程式撰寫的複雜度；再配合語言內建機制強化驗證環境中功能性覆蓋率的計算，讓工程師能將有限的時間作更有效率的運用。 串列式匯流排(USB)是現今科技產業中廣泛使用的一種規格，舉凡各種產品皆可以此介面與電腦連接通訊。有鑑於此，本文以目前(西元2010年)最新的USB3.0規格為例，設計並實現一個具有前述各項優勢的驗證環境，希望可以對積體電路設計製造過程提供正面的助益，也提供一個相關應用領域可以互相參照與比較優缺的實例。 | zh_TW |
| dc.description.abstract | The complexity of digital electronic circuit is growing dramatically these years, making verification process, which is considered the major bottleneck, more challenging. Moreover, the rapid renew of various technologies is forcing IC industry to shorten the time-to-market of a product, which means to compress the time period of designing, verification, and tape-out process. To address this problem, an effective and comprehensive verification environment is necessary.
In this thesis, we design and implement a layered verification environment based on object oriented language, SystemVerilig. Utilizing the Constrained-Random Stimulus Generation property in SystemVerilig, the stimulus is generated randomly in a restricted subset, thus it not only raises the probability of hitting a bug but also makes programming task easier. The object oriented characteristic and built-in functional coverage mechanism makes this environment more efficient and reliable. Universal Serial Bus is a commonly used interconnect interface, so we use it as an example to design and implement a verification environment. Hoping to offer some effort to IC industry and giving out an implementation for related studies to compare the pros and cons, we present this work. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:13:56Z (GMT). No. of bitstreams: 1 ntu-99-R97943157-1.pdf: 6585063 bytes, checksum: 3a4dc016849541e4fc21a90e18f855ba (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 口試委員審定書 I
誌謝 II 摘要 III ABSTRACT IV CONTENTS V LIST OF FIGURE X CHAPTER 1 INTRODUCTION 1 1.1 VERIFICATION 1 1.2 FUNCTIONAL VERIFICATION 2 1.3 SIMULATION-BASED VERIFICATION 3 1.4 BUS FUNCTIONAL MODEL (BFM) 4 1.5 GENERATION OF INPUT VECTOR 4 1.6 CONSTRAINED-RANDOM STIMULUS 5 1.7 TYPES OF COVERAGE METRIC 5 1.7.1 Code Coverage 5 1.7.2 Assertion Coverage 6 1.7.3 Toggle Coverage 6 1.7.4 Functional Coverage 6 1.8 COMPONENTS OF VERIFICATION ENVIRONMENT 7 1.9 MOTIVATION 8 CHAPTER 2 USB 3.0 SYSTEM SPECIFICATION OVERVIEW 9 2.1 PHYSICAL LAYER 9 2.1.1 Link Initialization and Training 12 2.1.2 Sending and Receiving of Data 14 2.1.3 Low Frequency Periodic Signaling (LFPS) 15 2.2 LINK LAYER 15 2.3 PROTOCOL LAYER 18 2.4 DEVICE FRAMEWORK 19 2.5 DATA FLOW MODELS 22 2.5.1 Control Transfer 24 2.5.2 Bulk Transfer 24 2.5.3 Interrupt Transfer 25 2.5.4 Isochronous Transfer 25 CHAPTER 3 VERIFICATION ENVIRONMENT 26 3.1 ARCHITECTURE OVERVIEW 26 3.2 IMPLEMENTATION 29 3.2.1 Test Suite 30 3.2.2 Bus Functional Model (BFM) 30 3.2.3 Scoreboard/Checker 31 3.2.4 Assertion and Functional Coverage 32 3.3 PROGRAMMING INTERFACE 32 3.3.1 Callbacks 32 3.3.2 Class Methods 35 3.3.3 Packet Manipulation Based on Event Notification 35 3.3.4 More Methods 36 3.4 DATA MOVEMENT 37 3.4.1 Transaction 37 3.4.2 Bulk 37 3.4.3 Control 38 3.4.4 Isochronous 39 3.4.5 Interrupt 40 3.5 PACKET 41 3.6 SUPERSPEED TRACKER FILES 42 3.7 SUPERSPEED SYMBOL TRACKER 43 3.8 ASSERTIONS 44 3.9 DEVICE FRAMEWORK 45 3.10 DEVICE DESCRIPTOR CLASSES 46 3.11 ENUMERATION 46 3.11.1 Bypass Bus Enumeration 48 3.12 DEVICE FRAMEWORK COMMANDS 48 3.13 CONTROLLING LINK LAYER BEHAVIOR 58 3.14 CONTROLLING PHYSICAL LAYER BEHAVIOR 59 CHAPTER 4 EXPERIMENTAL RESULT 60 4.1 TEST PLANE 60 4.2 MEASUREMENT OF FUNCTIONAL COVERAGE 61 CHAPTER 5 CONCLUSION AND FUTURE WORK 64 5.1 CONCLUSION 64 5.2 FUTURE WORK 64 REFERENCE 66 | |
| dc.language.iso | en | |
| dc.subject | 通用序列匯流排 | zh_TW |
| dc.subject | 硬體驗證 | zh_TW |
| dc.subject | 功能性驗證 | zh_TW |
| dc.subject | 驗證環境 | zh_TW |
| dc.subject | Functional Verification | en |
| dc.subject | Verification Environment | en |
| dc.subject | USB | en |
| dc.subject | Hardware Verification | en |
| dc.title | 第三代通用序列匯流排之功能性驗證環境設計及實作 | zh_TW |
| dc.title | Functional Verification Environment for Universal Serial Bus 3.0 | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆,顏嗣鈞,袁世一,呂學坤 | |
| dc.subject.keyword | 硬體驗證,功能性驗證,驗證環境,通用序列匯流排, | zh_TW |
| dc.subject.keyword | Hardware Verification,Functional Verification,Verification Environment,USB, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2010-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-99-1.pdf 未授權公開取用 | 6.43 MB | Adobe PDF |
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