基於超大規模統一記憶體系統之跨層級設計

Abstract

隨著大數據時代的到來，應用程式所需要的記憶體容量的成長速度已經超過DRAM記憶體所能提供，並且大型的DRAM記憶體也帶來了極高的漏電流與硬體的成本考驗。為了解決這樣的問題，異質性記憶體(Unified Memory)被提出來置換純DRAM的主記憶體用於資料密集的應用。異質性記憶體通常包含著少量且高速的DRAM與大量低成本的非揮發性記憶體，這些揮發性記憶體中又以快閃記憶體最為成熟。但是快閃記憶體相較於DRAM有著極高的存取延遲，為了避免主記憶體的存取效能被嚴重的影響，通常會使用DRAM當作快閃記憶體的快取。將最近常用的資料存取於DRAM，而比較不常用的資料則存放於快閃記憶體中。主記憶體層級需要兼顧著存取的效能與維護的成本，我們提出了兩個跨層級的設計是基於CPU的異質性主記憶體，第一個研究主要是在記憶體模組內部如何優化存取效能並降低管理維護成本，而第二個研究則是利用作業系統與記憶體模組兩者的資訊交換來更進一步降低維護成本並優化存取效能。除此之外，我們第三個研究則是基於GPU的異質性主記憶體設計，利用排程資訊來預先搬移資料於快閃記憶體與DRAM之間。一系列的實驗證明我們的設計可以有效改善存取效能與兼顧維護成本。

In the big data era, data-intensive applications have a growing demand for the capacity of DRAM main memory, but the frequent DRAM refresh, high leakage power, and high unit cost bring serious design issues on scaling up DRAM capacity. To address this issue, unified memory system, which is a heterogeneous memory system, becomes a possible alternative to replace DRAM as main memory in some data-intensive applications. Unified memory system that consists of a small-sized high-speed DRAM and a large-sized low-cost non-volatile memory (i.e., flash memory) has the serious performance issue on accessing data stored in the flash memory because of the huge performance gap between DRAM and flash memory. However, there is limited room to adopt a complex caching algorithm for using DRAM as the cache of flash memory in unified memory system because a complex caching algorithm itself would already cause too much performance degradation on handling each request to access unified memory system. In this paper, we present two cross-layer designs to boost CPU-based unified memory system performance by minimizing the cache management overhead and reducing the frequencies to access flash memory. The first design is to improve the performance in device level, and the second design is hardware and software co-design by the interactivity of OS and device layers. In addition, we also present one cross-layer design for GPU-based unified memory system to improve the performance of GPU device. A series of experiments was conducted based on popular benchmarks, and the results demonstrate that the proposed designs can effectively improve the performance of unified memory system.