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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Guan-Yu Su | en |
dc.contributor.author | 蘇冠宇 | zh_TW |
dc.date.accessioned | 2021-06-08T03:40:59Z | - |
dc.date.copyright | 2019-07-10 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-06-30 | |
dc.identifier.citation | [1] J. Zhu, R. Nandwana, G. Shu, A. Elkholy, S.-J. Kim, and P. Hanumolu, “A 0.0021 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 338-339.
[2] B. Drost, M. Talegaonkar, and P. Hanumolu, “Analog filter design using ring oscillator integrators,” IEEE Journal of Solid-State Circuits, vol. 47, no.12, pp. 3120-3129, Dec. 2012. [3] J. Chuang and H. Krishnaswamy, “A 0.0049 mm2 2.3 GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOM,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 328-329, Feb. 2017. [4] X. Gao, E. Klumperink, M. Bohsali, and B. Nauta, “A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,” IEEE Journal of Solid-State Circuits, vol. 44, no.12, pp. 3253-3263, Dec. 2009. [5] K. Sundaresan, P.E. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE Journal of Solid-State Circuits, vol. 41, no. 2, pp. 433-442, Feb. 2006. [6] P.-Y. Wang, S.-P. Chen, and P. Chen, “Timing orthogonal capacitance multiplication technique for PLL,” IEEE Sym. VLSI Circuits Dig. Tech. Papers, pp. 162-163, June, 2007. [7] W. F. Egan, Frequency Synthesis by Phase Lock, New York: Wiley & Sons, 1981. [8] H. Roder, “Amplitude, phase, and frequency modulation,” Proc. Inst. Radio Eng., vol. 19, no. 12, pp. 2145-2176, Dec. 1931. [9] M. Song, T. Kim, J. Kim, W. Kim, S.-J. Kim, and H. Park, “A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2015. [10] J. Liu, T.-K. Jang, Y. Lee, J. Shin, S. Lee, T. Kim, J. Park, and H. Park, “A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase- selection fractional frequency divider,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 268-269, Feb. 2014. [11] Y.-C. Huang, C.-F. Liang, H.-S. Huang, and P.-Y. Wang, “A 2.4GHz ADPLL with digital–regulated supply-noise-insensitive and temperature-self- compensated ring DCO,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 270-271, Feb. 2014. [12] T.-K Jang, X. Nan, F. Liu, J. Shin, H. Ryu, J. Kim, T. Kim, J. Park, and H. Park, “A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase-locked loop using a phase-interpolating phase-to-digital converter,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 254-255, Feb. 2013. [13] M. Mercandelli, M. Mercandelli, L. Grimaldi, L. Bertulessi, C. Samori, A. L. Lacaita, and S. Levantino, “A background calibration technique to control the bandwidth of digital PLLs,” IEEE Journal of Solid-State Circuits, vol. 53, no.11, pp. 3243-3255, Nov. 2018. [14] C.-H. Chiang, C.-C. Huang, and S.-I. Liu, “A digital bang-bang phase-locked loop with bandwidth calibration,” IEEE Asian Solid-State Circuits Conf. (ASSCC) Dig. Tech. Papers, pp. 173-176, Nov. 2015. [15] H. Xu and A. A. Abidi, “Design methodology for phase-locked loops using binary (bang-bang) phase detectors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 7, pp. 1637–1650, Jul. 2017. [16] T.-K. Kuan and S.-I. Liu, “A bang-bang phase-locked loop using automatic loop gain control and loop latency reduction techniques,” IEEE Journal of Solid-State Circuits, vol. 51, no.4, pp. 821-831, Apr. 2016. [17] S. Jang, S. Kim, S.-H. Chu, G.-S. Jeong, Y. Kim, and D.-K. Jeong, “An optimum loop gain tracking all-digital PLL using autocorrelation of bang-bang phase-frequency detection,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 9, pp. 836–840, Sep. 2015. [18] S. Höppner, J. Partzsch, J. Neumann, R. Schüffny, and C. Mayr, “A calibration technique for bang-bang ADPLLs using jitter distribution monitoring,” IEEE Transactions on Very Large Scale Integration Systems, vol. 24, no. 12, pp. 3548-3552, Dec. 2016. [19] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13-m CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006. [20] B. Razavi, “The StrongARM latch [a circuit for all seasons],” IEEE Solid-State Circuits Mag., vol. 7, no. 2, pp. 12-17, Jan. 2015. [21] D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong, “A 0.3-1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller,” IEEE Journal of Solid-State Circuits, vol. 45, no.11, pp. 2300-2311, Nov. 2010. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21646 | - |
dc.description.abstract | 這篇論文的主題主要分為兩個部分,第一部分實現了一個具背景頻率校正之基於時域積分器之鎖相迴路。利用單個時域積分器,頻寬內的相位雜訊以及功率效能均能提升;使用背景頻率校正方法可以使鎖相迴路容忍製程、供應電壓、溫度的變異。引進時序錯綜的方法可以讓參考突波有效下降。量測到的相位雜訊在距離主頻100 kHz、1 MHz、10 MHz下分別為-100 dBc/Hz、-108 dBc/Hz、-110 dBc/Hz。方均根值抖動量為1.5 ps。此鎖相迴路的有效面積與功耗分別為0.0011 mm2以及1.22 mW,雜訊的品質因數為-235.6 dB。
第二部分實現了一個數位鎖相迴路。提出的自動迴路增益校正電路使用頻譜平衡的方法,利用偵測數位相位頻路偵測器輸出的高頻與低頻的成分來調整迴路頻寬使得整體的數位鎖相迴路有最小的方均根雜訊。在沒有供應電壓雜訊的情況下,量測到的相位雜訊在距離主頻100 kHz、1 MHz、10 MHz下分別為-90 dBc/Hz、-95 dBc/Hz、-101 dBc/Hz,其方均根雜訊為3.64 ps。在有5 mVPP 及300 kHz的供應電壓雜訊下,使用提出的自動迴路增益電路可以使方均根雜訊值從8.5 ps降到5.1 ps。此數位鎖相迴路的面積與功耗分別為0.016 mm2以及1.5 mW。 | zh_TW |
dc.description.abstract | This thesis consists of two parts. The first part implements a phase-locked loop (PLL) using a single-ring-oscillator-based integrator with background frequency calibration. By introducing the single-ring-oscillator-based integrator, the in-band phase noise and the power efficiency of the PLL are improved. With background frequency calibration, it allows this PLL to tolerate process, supply voltage, and temperature variations. Moreover, the reference spur will be improved by using timing orthogonal scheme. The measured phase noise is -100dBc/Hz, -108dBc/Hz and -110dBc/Hz at the offset frequencies of 100kHz, 1MHz, and 10MHz, respectively. The integrated root-mean-square jitter is 1.5ps and achieves a figure-of-merit of -235.6dB. This PLL is fabricated in 40-nm CMOS process which occupies an active area of 0.0011mm2. Its power consumption is 1.22mW from a 1V supply voltage.
The second part implements a digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC). The ALGC uses a spectrum-balancing technique detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. The power consumption of the DPLL is 1.5mW from a 1V supply voltage. Without the power supply noise, the measured phase noise is -90dBc/Hz, -95dBc/Hz and -101dBc/Hz at the offset frequency of 100kHz, 1MHz and 10MHz, respectively. The integrated RMS jitter is 3.64ps, which is translated to have a figure-of-merit of -227dB. With a 5mVPP and 300kHz sinusoidal power supply noise, the RMS jitter is reduce from 8.5ps to 5.1ps by using the proposed ALGC. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T03:40:59Z (GMT). No. of bitstreams: 1 ntu-108-R05943173-1.pdf: 5042486 bytes, checksum: 5dc72e86e60eff10da43400d7fe32a8e (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 1. Introduction 1
1.1 Motivation 1 1.2 Overview 2 2. A Phase-Locked Loop Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration 5 2.1 Motivation 5 2.2 Frequency Calibration 6 2.2.1 PVT Effects on PLL Using Time-Based Integrator 6 2.2.2 Frequency Calibration 11 2.3 Circuit Description 14 2.3.1 Overall PLL Architecture 14 2.3.2 CCRO 15 2.3.3 Single-to-Differential Buffer, Dead-Zone and V2I Converter 16 2.3.4 Timing Orthogonal Technique 17 2.3.5 PLL Loop Dynamics 19 2.4 Experimental Results 24 2.5 Performance Summary 33 3. A Digital Phase-Locked Loop With Adaptive Loop Gain Controller Using Spectrum-Balancing Technique 35 3.1 Motivation 35 3.2 Review of Noise in DPLLs 36 3.2.1 Loop Transfer Function 36 3.2.2 Jitter Calculations 42 3.3 Output Power Spectrum of BBPFD 45 3.4 Circuit Description 48 3.4.1 DPLL with ALGC 48 3.4.2 Power Detector Incorporating Two Filters 51 3.4.3 StrongARM Latch 53 3.4.4 DCO 55 3.5 Experimental Results 55 3.6 Performance Summary 64 4 Conclusion and Future Work 67 4.1 Conclusion 67 4.2 Future Work 68 Bibliography 69 | |
dc.language.iso | en | |
dc.title | 基於時域積分器之鎖相迴路與數位鎖相迴路之迴路增益最佳化 | zh_TW |
dc.title | A Phase-Locked Loop Using a Single-Ring-Oscillator-Based Integrator and a Digital Phase-Locked Loop With Adaptive Loop Gain Controller | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊清淵(Ching-Yuan Yang),李泰成(Tai-Cheng Lee),黃柏鈞(Po-Chiun Huang),郭泰豪(Tai-Haur Kuo) | |
dc.subject.keyword | 鎖相迴路,時域積分器,頻率校正,數位鎖相迴路,自動迴路增益控制器,雜訊最小化, | zh_TW |
dc.subject.keyword | phase-locked loop,time-based integrator,frequency calibration,digital phase-locked loop,adaptive loop gain controller,jitter minimization, | en |
dc.relation.page | 71 | |
dc.identifier.doi | 10.6342/NTU201901129 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2019-07-01 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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