利用機器學習方法偵測受動態電壓降影響之危急時序路徑

Abstract

一些時序限制（timing constraint）容易導致大型積體電路（large integrated circuits）或是系統單晶片（system-on-a-chip）之工作頻率下降，且經常因動態電壓降（dynamic voltage drop）導致違反建立時間（setup timing violation），可稱之為最大時序誤差（maximum timing pushout）。此問題於鰭式場效應電晶體設計（FinFET designs）中會更加嚴重，本論文目的為利用機器學習方法來預測危急時序情境 （critical scenarios），其中危急時序情境為包含了許多時序路徑（timing paths）的資料，使其更快速能進一步執行動態電壓降分析，以及危急時序路徑（critical timing path）之預測，使其能進而執行更佳準確之時序分析；其流程是先利用分類器去預測時序路徑之危急程度，接著去預測最危急的那些時序路徑之排名，最後算出情境之個別排名，而前幾名即為危急時序情境；接著危急時序情境中的時序路徑經由動態電壓降分析後，再利用分類器去預測時序路徑之危急程度，即可進行更準確之時序分析；以機器學習的方法，其最佳的分類模型效果能夠達到平均約90%準確率，對於前五名危急時序情境亦能夠達到約80%的命中率。

Timing constrain will reduce operational frequency of large integrated circuits or system-on-a-chip, and it is often caused by setup timing violation which would be influenced by dynamic voltage drop, can be referred to as maximum timing pushout. This problem is exacerbated in the FinFET designs. This thesis proposes a method using machine learning techniques to predict critical scenarios quickly for analyzing dynamic voltage drop and critical timing paths predictor for accurate timing analysis. First, we use a classification model to predict critical level of timing paths, and use a regression model or a ranking model to predict ranking of the critical timing paths afterwards. Next, we can determine the critical scenarios for analyzing dynamic voltage drop. After the analysis, we use the classification model to predict critical level of timing paths which is similar to the first step. In our method, the best classification model can achieve about 90% accuracy, and 80% of hit-rate in Top-5 critical scenarios predicting.