請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21088
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Tung-Cheng Lin | en |
dc.contributor.author | 林東澄 | zh_TW |
dc.date.accessioned | 2021-06-08T03:26:50Z | - |
dc.date.copyright | 2021-02-22 | |
dc.date.issued | 2021 | |
dc.date.submitted | 2021-02-02 | |
dc.identifier.citation | [1] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [2] M. Furuta, M. Nozawa, and T. Itakura, “A 10bit, 40MS/s, 1.21mW Pipelined-SAR ADC Using Single-Ended 1.5bit/cycle Conversion Technique ,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1360–1370, Dec. 2011. [3] H. Huang, H. Xu, B. Elies, and Y. Chiu, “A Non-Interleaved 12b 330MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation ,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3235–3247, Dec. 2017. [4] C. Liu, S. Chang, G. Huang, and Y. Lin, “ A 10bit 50MS/s SAR ADC With a Monotonic Capacitor Switching Procedure ,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010. [5] C. C. Lee and M. P. Flynn, “ A SAR Assisted Two Stage Pipeline ADC ,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859–869, Apr. 2011. [6] T. M. et al., “ A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using An Interleaved Subranging Pipeline A/D Converter ,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1840–1850, Nov. 1998. [7] J. T. et al., “ A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching ,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1382–1398, June 2015. [8] A. M. Abo and P. R. Gray, “ A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter ,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. [9] Y.-Z. Lin, C.-H. Tsai, S.-C. Tsou, and C.-H. Lu, “ A 8.2mW 10-b 1.6GS/s 4× TI SAR ADC With Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16nm CMOS ,” in Symp. VLSI Circuits Dig., pp. 1–2, June 2016. [10] H. Huang, L. Du, and Y. Chiu, “ A 1.2GS/s 8-bit Two-Step SAR ADC in 65nm CMOS With Passive Residue Transfer ,” Asian Solid-State Circuits Conference., pp. 1–4, Nov. 2015. [11] R. Reeder, “ Transformer-Couple Front-End for Wideband A/D Converters ,” Analog Dialogue, vol. 39, no. 2, Apr. 2005. [12] R. Reeder and J. Caserta, “ Wideband A/D Converters Front-End Design Considerations II: Amplifier or Transformer Drive for The ADC? ,” Analog Dialogue, vol. 41, no. 1, Feb. 2007. [13] H. H. et al., “ A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC ,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 543–555, Feb. 2015. [14] S. Lee, A. P. Chandrakasan, and H. Lee, “ A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration ,” in ISSCC Dig. Tech. Papers, pp. 384–385, Feb. 2014. [15] A. R. et al., “ A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS ,” in ISSCC Dig. Tech. Papers, pp. 62–64, Feb. 2019. [16] B. Murmann, “ ADC Performance Survey 19972019 ,” [Online]. Available: https://web.stanford.edu/ murmann/adcsurvey.html,. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21088 | - |
dc.description.abstract | 隨著5G世代的來臨,高速和高解析度的類比數位轉換器已經成為了不可或缺的部分。傳統的逐次逼近類比數位轉換器架構雖然可以達到中等解析度和和很高的電源節省效率,但整體的轉換速度會受到其漸進式的過程所限制;時間交錯系統類比數位轉換器能夠有效的提升逐次逼近類比數位轉換器的速度,但會有諸多的問題導致整體效能的下降,例如:取樣的相位誤差、通道的元件誤差、增益誤差......等。因此,電路中往往需要複雜的校正系統,言而總之,管線式逐次逼近類比數位轉換器成為了一個比較好的選擇。然而,傳統上的管線式逐次逼近類比數位轉換器在轉換過程中,需要留一段時間供給放大器所使用,使轉換速率下降。本篇即使用了能夠讓轉換過程與放大過程同時進行的技巧,解放了管線式逐次逼近類比數位轉換器的速度限制,此外,本篇還開發了一個壓變電容為基底的開迴路動態式放大器來改善線性度,使放大器能夠應付高達10位元的逐次逼近類比數位轉換器。本篇最後達到一個通道十位元、一億赫茲取樣頻率,在Nyquist輸入頻率下信噪失真比(SNDR)達41.34分貝、電源功耗為9.4毫瓦。 | zh_TW |
dc.description.abstract | Along with 5G generations coming, high-speed and high-resolution analog - to - digital converters (ADCs) are the essential building blocks. Classical successive - approximation - register (SAR) ADC architectures can reach moderate resolution and high power efficiency, but the speed is limited by their serial decision-making process. Although the time-interleaved ADCs can really speed up the SAR ADC architectures, multiphase error, channel mismatch and gain error degrade the performance. Therefore, intensive calibration circuits are required. Alternatively, pipelined SAR architectures are the applicable choices. The conventional pipelined SAR ADCs need to reserve sufficient time for the residue amplifier. In this work, a technique that allows residue conversion and partial bit conversion in parallel is proposed in the pipelined SAR ADC to lessen timing constraint. Furthermore, a varactor-based dynamic amplifier is adopted to improve linearity for 10-b accuracy. The single channel prototype reaches 10-bit 1GS/s with SNDR 41.34dB at a Nyquist input consuming 9.4mW. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T03:26:50Z (GMT). No. of bitstreams: 1 U0001-0102202113404700.pdf: 105789382 bytes, checksum: 7776b9efaf0bb5ba5296ac934ca6de0f (MD5) Previous issue date: 2021 | en |
dc.description.tableofcontents | Acknowledgements ii 摘要 iii Abstract iv 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamental 3 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Architectures of Analog-to-Digital Converter . . . . . . . . . . . . . . . 8 2.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.2 Subrange ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.3 Successive Approximation ADC . . . . . . . . . . . . . . . . . . 10 2.3.4 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.5 Time-Interleaved ADC . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.6 Pipelined SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Dynamic Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 The Proposed Architecture and Building Blocks 16 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Proposed Pipelined SAR ADC Overview . . . . . . . . . . . . . . . . . 17 3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 Architecture And The Proposed Techniques . . . . . . . . . . . . 18 3.2.3 Proposed Dynamic Amplifier . . . . . . . . . . . . . . . . . . . 20 3.3 SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 Capacitor Switching Procedure . . . . . . . . . . . . . . . . . . . 24 3.3.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3 Bootstrapped Switch . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.4 Capacitive DAC . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.5 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.6 Overlapped Control Logic . . . . . . . . . . . . . . . . . . . . . 28 3.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 Design Considerations 31 4.1 CDAC Unit Capacitance Consideration . . . . . . . . . . . . . . . . . . 31 4.1.1 KT/C Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.2 Mismatch Consideration . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.1 Comparator Noise . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.2 Dynamic Amplifier Noise . . . . . . . . . . . . . . . . . . . . . 35 4.3 Offset Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 Non-linearity of Charge Sharing Technique . . . . . . . . . . . . . . . . 38 4.5 Biasing of The Dynamic Amplifier . . . . . . . . . . . . . . . . . . . . . 41 5 Measurement 44 5.1 Print Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2 Chip Die-photo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4 Analog Front-End Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5 Measured Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 Conclusion 53 6.1 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bibliography 55 | |
dc.language.iso | en | |
dc.title | 使用可變電容為基礎的殘餘值放大器的平行切換管線式循序漸進類比數位轉換器的分析與設計 | zh_TW |
dc.title | Design and Analysis of a Parallel Conversion Pipelined-SAR ADC with Varactor Based Residue Amplifier | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),劉深淵(Shen-Iuan Liu),黃柏鈞(Po-Chiun Huang) | |
dc.subject.keyword | 管線式逐次逼近類比數位轉換器,開迴路動態式放大器,高速, | zh_TW |
dc.subject.keyword | Pipelined-SAR ADC,Dynamic amplifier,High-speed, | en |
dc.relation.page | 56 | |
dc.identifier.doi | 10.6342/NTU202100320 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2021-02-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
U0001-0102202113404700.pdf 目前未授權公開取用 | 103.31 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。