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標題: | CMOS寬頻功率放大器及脈衝調變功率放大器 CMOS Wideband Power Amplifier and Pulse Modulated Power Amplifier |
作者: | Shan-En Chang 張善恩 |
指導教授: | 陳怡然 |
關鍵字: | 堆疊式電晶體,寬頻,功率放大器,網路合成,開關鍵控,脈衝調變器,高效率,米勒電容,脈衝調變功率放大器, Stacked Transistors,Wideband,Power Amplifier,Network Synthesis,On-Off Keying,Pulse Modulator,High Efficiency,Miller capacitance,Pulse Modulator Power Amplifier, |
出版年 : | 2016 |
學位: | 碩士 |
摘要: | 隨著通訊系統的發展,民間業者不斷地爭取頻段商業化,因此,美國聯邦通訊委員會(FCC)將900 MHz、2.4 GHz以及5.8 GHz三段頻帶,稱為工業科學醫療頻帶(ISM Band)並開放給民間使用。為了能夠同時傳送多頻帶的訊號,傳送端必須具有一個寬頻功率放大器來供使用。
在通訊系統中,常可見到各種調變技術運用於傳送端,而射頻功率放大器在通訊系統中扮演相當重要的角色,是發射機的主要組成部分,其消耗的能量為射頻收發機中的60 ~ 90 %,因此功率放大器消耗程度的效率高低與否,就變得額外重要。 本論文主要分為兩個部分,皆採用0.13微米互補式金屬氧化物半導體(CMOS)製程來製作全積體化的CMOS功率放大器。為了克服CMOS的低崩潰電壓以及提高輸出功率與效率的特性,本論文皆使用堆疊式電晶體(Stacked Transistors)來設計功率放大器。 在論文的第一部分,設計一個應用於ISM band的2 ~ 6 GHz高功率與高效率之寬頻單級功率放大器,架構為堆疊四顆電晶體的功率放大器,並採用網路合成(Network Synthesis)的寬頻匹配方法。此功率放大器,由模擬結果得知,其小訊號增益(S21)的1 dB 頻寬為2 ~ 6 GHz以及3 dB頻寬為 1.6 ~ 6.3 GHz,其1 dB頻寬內,輸出1 dB壓縮功率點(P_1dB)為28.1 ~ 29.1 dBm以及此時的PAE為35.3 ~ 48.66 %,P_sat 為30.9 ~ 31.9 dBm以及此時的PAE為46.6 ~ 50.2 %。其頻寬內包含ISM Band的2.4 GHz(2400 ~ 2500 MHz)及5.8 GHz(5725 ~ 5875 MHz)等兩個頻帶。 在論文的第二部分,脈衝調變功率放大器,架構為一個使用開關鍵控(On-Off Keying, OOK)技術的脈衝調變器及一個雙級高效率功率放大器結合的脈衝調變功率放大器,其中,脈衝調變器由模擬得知,S11與S22小於 – 10 dB的頻寬為590 MHz,S21的3 dB頻寬為500 MHz(1700 ~ 2200 MHz),最低隔離度為65.42 dB;而整體電路在1.9 GHz時,由模擬結果得知,當輸入功率為 – 6 dBm時,其轉換功率增益為34.0 dB,輸出功率為28.0 dBm,此時的PAE為58.9 %。 As the development of communication systems, the industry continues to request more frequency bands. Therefore, the FCC releases 900 MHz, 2.4 GHz and 5.8 GHz bands as the industrial scientific medical band(ISM Band)for openly use. In order to simultaneously transmitting signals in multiple frequency bands, there should be a broadband power amplifier in a transmitter. In the communication systems, there are variety of modulation techniques. The radio frequency power amplifier is an important component of the transmitter and plays a crucial role in communication systems. It dominates about 60% to 90% of the energy consumptions in the RF transceiver. Therefore, the power-added efficiency, affecting the degree of the power consumption, is distinctly important. This thesis presents the CMOS power amplifiers that are implemented in 0.13 μm CMOS technology. In order to overcome CMOS transistors’ low breakdown voltage and improve the power and efficiency, this thesis adopts the stacked transistors to design power amplifier. The first wideband PA is one stage with, high power and high efficiency for ISM band. Circuit architecture uses four-stacked transistors and network synthesis broadband matching. From the simulation, this PA achieves a 1-dB bandwidth of 2 to 6 GHz and 3-dB bandwidth of 1.6 to 6.3 GHz. In the 1-dB bandwidth, this PA achieves P1dB of 28.1 to 29.1 dBm and PAE of 35.27 to 48.66 %;Psat of 30.9 to 31.9 dBm and maximum PAE of 46.61 to 50.15 %. The CMOS PA is able to cover ISM Band 2.4 GHz(2400 ~ 2500 MHz)and 5.8 GHz(5725 ~ 5875 MHz). The second part of PA is CMOS pulse modulation power amplifier with CMOS pulse modulator, which uses on-off keying technology, and two-stage high efficiency power amplifier. From the simulation, this OOK modulator achieves S11 and S22, less than - 10 dB, with 590 MHz bandwidth. The 3-dB bandwidth of S21 is 500 MHz(1700 ~ 2200 MHz). This pulse modulated power amplifier achieves a power gain of 34.0, output power of 28.0 dBm and PAE of 58.9 % when frequency is 1.9 GHz and input power is – 6 dBm. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21063 |
DOI: | 10.6342/NTU201603857 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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