高切換頻率的數位控制直流對直流降壓型轉換器設計

Abstract

在一個積體電路系統中，電源管理晶片扮演了相當重要的角色，其負責提供一個穩定的電壓源，一個理想上不隨電池電壓或是輸出電流而有所變化的電壓源；然而，電源管理晶片所需的外掛電感以及電容，佔據了相當大的使用空間。本論文提出了一個微小型電源轉換器，用以減小外掛元件的數量以及大小。 本作品採用台積電90奈米製程，實作並量測一個同時使用數位控制以及高操作頻率的方式，達到將補償器外掛元件完全移除，並且大幅降低所需元件數值。另外藉由數位控制的方式，完全排除設計誤差放大器的頻寬問題。使用二進制權延遲線數位脈衝寬度調變器，將原本六十四轉一數據選擇器的面積節省下來。四位元窗型快閃類比數位轉換器有效節省百分之八十七點五的能源消耗及面積，並且將類比數位轉換器的延遲時間減至最低。在五千萬赫茲的操作頻率下，本作品使用一百奈米亨利的電感及一百奈米法拉的電容，輸入電壓為一點二伏特，輸出電壓為零點八伏特，實現一能源轉換效率高達百分之八十二的微小型基於電感之數位控制高切換頻率降壓型直流對直流電源轉換器。

Power management IC (PMIC) is a critical building block in integrated circuits for providing stable supply voltages, which ideally don’t change with the battery voltage and the output load current. However, due to the limited area, large inductors and capacitors used in the PMICs are not preferred in modern portable devices. In this thesis, a compact dc-dc power converter is proposed to minimize the off-chip components sizes. In this work, an inductor-based high-switching frequency digitally-controlled step-down dc-dc power converter with weighted delay-line DPWM is adopted to reduce the off-chip component sizes and eliminates the bandwidth restriction of the error amplifier. A 4-bit window-flash ADC is employed to save 87.5 % of the power and area and minimize the ADC latency. Meanwhile, the weighted delay-line DPWM successfully converts the digital code into time-domain duty cycle information without the redundant 64-to-1 MUX. Operating at 50 MHz switching frequency, a compact dc-dc power converter is realized with 100 nH inductor and 100 nF capacitor and the power conversion efficiency is as high as 82 %. The circuit has been implemented in TSMC 90 nm CMOS process.