低電壓次諧波注入鎖定式鎖相迴路設計於90奈米CMOS技術

Abstract

隨著物聯網的發展與進步，生醫積體電路的應用也越來越受到歡迎。但相關的應用受制於電池的壽命，因此低功耗的電路設計越來越顯為重要。如穿戴式裝置上的太陽能電池能夠提供0.5V電壓，而且根據國際半導體科技組織的報告，下一世代低功耗電路設計，其供應電壓將下降至0.5伏特。 在整個生醫積體電路系統中，鎖相迴路負責提供參考頻率。然而在低電壓環境下，電路的電流會變得更微弱，這將導致鎖相迴路的操作頻率受到限制；除此之外在低電壓環境中，相位雜訊效應也會變得更顯得明顯，使得電路效能變得更差。 在本論文中針對以上的兩個問題提出改善的設計。在供應電壓0.5伏特的限制下，將採用改良式的拔靴帶技術來提升震盪器的操作頻率。差動對拔靴帶技術不只可以增加的震盪器的振幅，也會增加電晶體驅動電流的能力，同時使用閘極切換技術來增加充電汞的操作區域。針對於相位雜訊提高的問題，採用注入鎖定技術來抑制振盪器的相位雜訊(phase noise)和抖動(jitter)。除了傳統的手動注入鎖定之外，自動注入鎖定技術也被採用在此設計。 本晶片計採用TSMC 90奈米製程實現低電壓次諧波注入式鎖相迴路，晶片面積為0.108mm2，在供應電壓為0.5伏特下，PLL的操作區間為330MHz至700MHz，功耗為333.5毫瓦。手動調整注入相位雜訊在位移1MHz和均方根抖動分別為 -106.56dBc/Hz和5.5ps。

Based on the advance of the Internet of Things (IOT), the applications of biomedical IC become popular. Due to the limits of electric power consumption by the battery, the issue related to low power design for circuits is more important. The 0.5V voltage can be provided by solar cell in portable devices. According to the reports proposed by International Technology Roadmap for Semiconductor (ITRS), supply voltage of general low-power circuits will be scaled down to 0.5V for the next generation applications. The phase-locked loop (PLL) is an essential circuit for providing a reference frequency signal in a system on chip (SOC). However, the current of circuit is lower under an intrinsic low-voltage environment, and operating frequency of PLL circuit is restricted. In addition, the phase noise of oscillator in PLL circuit is more significant in low voltage design. In this thesis, we proposed two methods to improve the problems of low voltage PLL. The modified bootstrapped technique is adopted to increase the operating frequency of the oscillator under supply voltage of 0.5V. The differential bootstrapped technique increases not only the swing of oscillator, but also the driving current of MOSFET. The gate-switch technique is then introduced to the charge pump in order to increase operation range. The injection-locked technique is adopted to suppress the noise and jitter of VCO. The traditional manual injection-locked is design in this work, besides, the automatic injection-locked is also realized. This work for low-power design is implemented in standard 90nm CMOS technologies. The core area is 0.108mm , and it is operated between 330MHz to 700MHz at 0.5V supply voltage with the locking range. The fabricated circuit is consumed a dc power of 333.5μW which is lower than general requirement. Under the manual injection-locked, the phase noise at 1MHz offset and RMS jitter are -106.56dBc/Hz and 5.5ps, respectively.