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標題: | 釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件介面特性之研究 The research on the interface properties of Y-GeO2/ (GeO2) / Ge MOSCAP |
作者: | Guan-Shiun Wang 王冠勛 |
指導教授: | 林浩雄(Hao-Hsiung Lin) |
關鍵字: | 鍺,釔摻雜氧化鍺,氧化物 (金屬) 沉積熱退火處理,金氧半電容元件, Germanium,Yttrium-doped Germanium Oxide,PDA,PMA,MOSCAPs, |
出版年 : | 2017 |
學位: | 碩士 |
摘要: | 本論文利用氧化物分子束磊晶系統 (Oxide MBE System) 成長氧化層,並製作成釔摻雜氧化鍺 (氧化鍺) / 鍺金氧半電容元件 (Metal – Oxide – Semiconductor Capacitor, MOSCAP) 進行量測與分析。我們改變釔摻雜氧化鍺的比例、成長時基板溫度並加入氧化層沉積後熱退火 (Post – Deposition Annealing, PDA) 與金屬沉積後熱退火 (Post – Metallization Annealing, PMA) 以得到最佳的元件電特性。
透過調整電子束蒸鍍之釔的電子束電流大小以改變不同比例的釔摻雜氧化鍺,我們發現釔成分與電導法 (Conductance Method) 所求得之介面缺陷密度 (Dit) 以及閘極漏電流有一最低點,當釔摻雜比例為27% 時 (Y/ (Ge+Y) = 27%) 有著最小的Dit和最小的閘極漏電流,且漏電流與的Dit成正相關。我們將27% 的釔摻雜氧化鍺進行PDA和PMA處理後,求得在室溫下量測釔摻雜氧化鍺/ 鍺金氧半電容元件之介面缺陷密度為 3.31 x 1011 (eV-1cm-2) ,閘極漏電流為6.2 × 10-9 (A/cm2),遲滯為0.91 (V) 。 我們在釔摻雜氧化鍺與鍺之間多長一層0.5 nm的氧化鍺後經過PDA與PMA處理,氧化鍺與鍺基板的介面缺陷密度以及遲滯均下降,但閘極漏電流卻上升約八千倍到5.0 x 10-5 (A/cm2)。因此,我們認為氧化鍺不適合經過高溫處理。 我們改變基板溫度成長氧化層,成長溫度越高所製成的半導體元件介面缺陷越少,與經過PDA處理後的現象相同。400℃下成長釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件並經過PMA處理其室溫下量測之介面缺陷密度為2.2 x 1011 (eV-1cm-2) ,閘極漏電流為3.0 x 10-9 (A/cm2),遲滯為0.28 (V) 。因此,我們推論400℃成長能使釔摻雜氧化鍺 (氧化鍺) 有著較佳的氧化層結構以及釔摻雜氧化鍺 (氧化鍺) 與鍺介面有較佳的鍵結,改善金氧半電容元件特性。 In this thesis, characteristics of Y-GeO2/ (GeO2) / Ge Metal-Oxide-Semiconductor capacitor (MOSCAP) grown by Oxide MBE System are investigated. To get the best performance of the device, Yttrium concentration and growth temperature of the oxide layer are adjusted and both post-deposition annealing (PDA) and post-metallization annealing (PMA) are carried out. By controlling the emission current of the e-beam evaporation, the Yttrium concentration (xY) in Y-GeO2 is adjusted. It is found that there is a positive correlation between gate leakage current and Dit calculated by conductance method. Besides, there exists a minimum value of both interface traps density (Dit) and gate leakage current at a xY of 27 percent. The 27 percent Y-GeO2/ Ge MOSCAP is measured at room temperature, with Dit of 3.3 x 1011 (eV-1cm-2), gate leakage current of 6.2 x 10-9 (A/cm2), and hysteresis of 0.91 (V) after the PDA and PMA were carried out. MOSCAP with an extra 0.5-nm-thick GeO2 between Y-GeO2 and Ge show lower Dit and hysteresis while the gate leakage current becomes about 8000 times larger to 5.0 x 10-5 (A/cm2) after PDA and PMA. Hence GeO2 is not suitable for high temperature treatments. Growth temperature of the oxide layer is adjusted and it is find that the Dit becomes lower as the temperature goes higher, which is similar to the behavior after PDA treatment. The 400°C grown Y-GeO2/ (GeO2) / Ge MOSCAP after PMA treatment is measured at room temperature, with Dit of 2.2 x 1011 (eV-1cm-2), gate leakage current of 3.0 x 10-9 (A/cm2), and hysteresis of 0.28 (V). We infer that the structure of Y-GeO2 (GeO2) layer and its bonding between Ge interface is improved by 400°C high temperature growth, and hence behaves better MOSCAPs characteristics. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20616 |
DOI: | 10.6342/NTU201702569 |
全文授權: | 未授權 |
顯示於系所單位: | 光電工程學研究所 |
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