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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20149Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 洪士灝 | |
| dc.contributor.author | Yi-Mo Ho | en |
| dc.contributor.author | 何翊模 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:40:57Z | - |
| dc.date.copyright | 2018-03-01 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-02-13 | |
| dc.identifier.citation | [1] F. Bellard. Qemu, a fast and portable dynamic translator. In USENIX Annual Technical Conference, FREENIX Track, pages 41–46, 2005.
[2] E. Berg, H. Zeffer, and E. Hagersten. A statistical multiprocessor cache model. In Performance Analysis of Systems and Software, 2006 IEEE International Symposium on, pages 89–99. IEEE, 2006. [3] K. Beyls and E. D’Hollander. Reuse distance as a metric for cache behavior. In Proceedings of the IASTED Conference on Parallel and Distributed Computing and systems, volume 14, pages 350–360, 2001. [4] D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. Fpga-accelerated simulation technologies (fast): Fast, full-system, cycle-accurate simulators. In Proceedings of the 40th Annual IEEE/ACM international Symposium on Microarchitecture, pages 249–261. IEEE Computer Society, 2007. [5] I. Coporation. SignalTap II with Verilog Designs. [6] I. Coporation. Using ModelSim to Simulate Logic Circuits in Verilog Designs. [7] I. Coporation. Using TimeQuest Timing Analyzer. [8] I. Coporation. Avalon® Interface Specifications, 2017. [9] J. Edler and M. D. Hill. Dinero iv trace-driven uniprocessor cache simulator. [10] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, pages 3–14. IEEE, 2001. [11] M. D. Hill and A. J. Smith. Evaluating associativity in cpu caches. IEEE Transactions on Computers, 38(12):1612–1630, 1989. [12] M. Jacobsen, D. Richmond, M. Hogains, and R. Kastner. Riffa 2.1: A reusable integration framework for fpga accelerators. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 8(4):22, 2015. [13] X. Pan and B. Jonsson. Modeling cache coherence misses on multicores. In Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, pages 96–105. IEEE, 2014. [14] D. L. Schuff, M. Kulkarni, and V. S. Pai. Accelerating multicore reuse distance analysis with sampling and parallelization. In Proceedings of the 19th international conference on Parallel architectures and compilation techniques, pages 53–64. ACM, 2010. [15] Y. S. Shao, S. L. Xi, V. Srinivasan, G.-Y. Wei, and D. Brooks. Co-designing accelerators and soc interfaces using gem5-aladdin. In Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on, pages 1–12. IEEE, 2016. [16] C.-H. Tu, H.-H. Hsu, J.-H. Chen, C.-H. Chen, and S.-H. Hung. Performance and power profiling for emulated android systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 19(2):10, 2014. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20149 | - |
| dc.description.abstract | 在硬體開發期間,如何讓軟體開發者可以在虛擬平台上快速與精確地程式分析,是當前很重要的研究議題。而FPGA有著能源節省、適合大量整數運算以及能夠反覆重組以適應不同的工作需求的好處,如此的結構同時擁有硬體的速度以及軟體的彈性,近年逐漸受到廣泛使用。本論文中,我們希望透過FPGA來加速我們實驗室的效能分析工具(VPMU)快取部分的模擬來讓使用者可以更快地對程式進行分析。 | zh_TW |
| dc.description.abstract | Before the hardware of a system is available, developers often use a virtual platform to develop software for the system. However, to deliver a fast and accurate simulation of systems is still an important issue that is open for research. And FPGA chips has many benefits such as high power-performance ratio, good at intensive integer operation and can be reconfigured to adapt to different workloads. Such structure has the performance of hardware and the flexibility of software. In the thesis, with FPGA, we accelerate the cache simulation part of VPMU and let user profile a program much faster. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:40:57Z (GMT). No. of bitstreams: 1 ntu-107-R04944039-1.pdf: 3709907 bytes, checksum: ee6878d44e77dbf108a6f9580df3b8ba (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 口試委員審訂書 i
致謝 ii 摘要 iii Abstract iv Chapter 1 Introduction 1 Chapter 2 Background and Relatedwork 3 2.1 QEMU and VPMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 RIFFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Avalon-ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 MOESI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 3 Implementation 9 3.1 Buffer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Cache Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 4C Miss Discrimination[11][2][13] . . . . . . . . . . . . . . . . . . . . . 13 3.5 Cache Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 4 Evaluations 18 4.1 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 5 Conclusion 23 Bibliography 24 | |
| dc.language.iso | en | |
| dc.title | FPGA加速硬體模擬 | zh_TW |
| dc.title | FPGA Accelerated Hardware Co-simulation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 施吉昇,涂嘉恆 | |
| dc.subject.keyword | FPGA,硬體加速, | zh_TW |
| dc.subject.keyword | FPGA,Hardware acceleration, | en |
| dc.relation.page | 25 | |
| dc.identifier.doi | 10.6342/NTU201800567 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2018-02-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
| Appears in Collections: | 資訊網路與多媒體研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-107-1.pdf Restricted Access | 3.62 MB | Adobe PDF |
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