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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Yi-An Chang | en |
| dc.contributor.author | 張亦安 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:38:16Z | - |
| dc.date.copyright | 2018-07-26 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2018-07-20 | |
| dc.identifier.citation | [1] J. Lee, A. George, and M. Je, “A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18μm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2016, pp. 106–107.
[2] J. Koo, K. S. Moon, B. Kim, H. J. Park, and J. Y. Sim, “A quadrature relaxation oscillator with a process-induced frequency-error compensation loop,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2017, pp. 94–95. [3] P. F. J. Geraedts, E. Tuijl, E. A. M. Klumperink, G. J. M. Wienk, and B. Nauta “A 90μW 12MHz relaxation oscillator with a -162dB FOM,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 348–349. [4] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 ppm/◦C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2047–2054, Jul. 2009. [5] M. Seok, G. Kim, D. Blaauw, and D. Sylvester, “A portable 2-transistor picowatt termperature-compensated voltage reference operating at 0.5 V,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2534–2545, Oct. 2012. [6] Y. T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 35, no.3, pp. 308–317, Mar. 2000. [7] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 151–154, Jan. 2003. [8] S. Jeong, Z. Foo, Y. Lee, J. Y. Sim, D. Blaauw, and D. Sylvester, “A fully-integrated 71 nW CMOS temperature sensor for low power wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1682–1693, Aug. 2014. [9] B. R. Gregoire and U.-K. Moon, “Process-independent resistor temperature-coefficients using series/parallel and parallel/series composite resistors,” in Proc. ISCAS, May 2007, pp. 2826–2829. [10] Y. H. Chiang and S. I. Liu 'A submicrowatt 1.1-MHz CMOS relaxation oscillator with temperature compensation,' IEEE Trans. Circuits Syst. II, Express Briefs, vol. 60, no. 12, pp. 837–841, Dec. 2013. [11] J. Lee, P. Park, S. H. Cho, and M. Je, “A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 106–107. [12] Y. K. Tsai and L. H. Lu, “A 51.3-MHz 21.8-ppm/◦C CMOS relaxation oscillator with temperature compensation,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 64, no. 5, pp. 490–494, May 2017. [13] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An on-chip CMOS relaxation oscillator with voltage averaging feedback,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1150–1158, June 2010. [14] Y. Cao, P. Leroux, W. De Cock, and M. Steyaert, “A 63,000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 186–187. [15] T. Tokairin, K. Nose, K. Takeda, K. Noguchi, T. Maeda, K. Kawai, and M. Mizuno, “A 280 nW, 100 kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme,” in Proc. IEEE Symp. VLSI Circuits, June 2012, pp. 16–17. [16] S. Jeong, I. Lee, D. Blaauw and D. Sylvester, “A 5.8 nW CMOS wakeup timer for ultra-low-power wireless applications,” IEEE J. Solid-State Circuits, vol. 50, no. 8, pp. 1754–1763, Aug. 2015. [17] J. Mikulić, G. Schatzberger and A. Barić, “A 1-MHz on-chip relaxation oscillator with comparator delay cancelation,” in Proc. ESSCIRC, Sep. 2017, pp. 95-98. [18] J. Wang, W. L. Goh, X. Liu and J. Zhou, “A 12.77MHz 31 ppm/◦C on-chip RC relaxation oscillator with digital compensation technique,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 63, no.11, pp. 1816-1824, Nov. 2016. [19] A. Paidimarri, D. Griffith, A. Wang, G. Burra, A. P. Chandrakasan, “An RC oscillator with comparator offset cancellation,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1866–1877, Aug. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19974 | - |
| dc.description.abstract | 這篇論文利用數位校正迴路改進兩個弛張式振盪器。第一個振盪器利用抗抖動技術達成較佳的相位雜訊。數位校正迴路用以校正NMOS閘極源極電壓的溫度變異。此外也實現晶載參考電壓以避免外給參考電壓。此振盪器在1.2V供應電壓下消耗157.8μW。量測的平均振盪頻率為13.4MHz。有無校正的振盪頻率溫度係數分別為193.15和1098.7ppm/○C，改善5.7倍。在100kHz偏移頻率下的相位雜訊優值為-154.4dB。
第二個振盪器利用兩個數位校正迴路調整振盪器的參考電壓，使振盪頻率與比較器延遲無關，避免其造成溫度變異。由於補償後的振盪頻率與電阻阻值相關，利用組合電阻降低此阻值的溫度係數。量測的平均振盪頻率為943.1kHz。此振盪器在0.9V供應電壓下消耗5.2μW。有無校正的振盪頻率溫度係數分別為93.88和618.17ppm/○C，改善6.6倍。在-10~100°C間的頻率變異小於±0.7%。振盪頻率隨供應電壓變化的敏感度為4.37%/V。 | zh_TW |
| dc.description.abstract | Two relaxation oscillators with digital compensation loops are presented in this thesis. The first design is a relaxation oscillator exploiting anti-jitter technique to achieve great phase noise performance. The digital compensation loop is introduced to compensate the temperature variation of the gate-source voltage of an NMOS transistor. On-chip voltage references are realized, avoiding any off-chip voltage reference. Consuming 157.8μW under a 1.2V supply, the oscillator has an average frequency of 13.4MHz. The measured TCs of the oscillation frequency with and without compensation are 193.15 and 1098.7ppm/○C, demonstrating a 5.7× improvement. The figure of merit with respect to phase noise is -154.4dB at 100kHz offset frequency.
The second design utilizes two digital compensation loops (DCLs) to adjust the reference voltage of the oscillator in order to make the oscillation frequency independent of the comparator delay, which would cause temperature variations. Since the compensated oscillation frequency is dependent on a resistance, the parallel/series composite resistors are implemented to minimize the temperature coefficient of the resistance. The measured average oscillation frequency is 943.1kHz. The whole oscillator consumes 5.2μW under a 0.9V supply. The measured TCs of the oscillation frequency with and without compensation are 93.88 and 618.17 ppm/○C, respectively. It achieves a TC improvement of 6.6×. The measured frequency variation is within ±0.7% from -10○C to 100○C by using the DCLs. The measured line sensitivity is 4.37%/V. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:38:16Z (GMT). No. of bitstreams: 1 ntu-106-R05943012-1.pdf: 3281624 bytes, checksum: 22bb9a7aaeb862d48664b267bc0e21ae (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 1. Introduction………………………………………………………… 1
1.1 On-chip Oscillators…….……………………………………. 1 1.2 Overview…………………………………………………….. 2 2. A Low Phase Noise Relaxation Oscillator with Temperature Compensation……………………………………………………… 4 2.1 Motivation…………………………………………………… 4 2.2 Circuit Description…………………………………………... 6 2.2.1 Overview of the Operation…………………………... 6 2.2.2 Proposed Oscillator………………………………….. 10 2.2.3 Voltage Reference.…………………………………… 14 2.2.4 Temperature Insensitive Current Source…………….. 16 2.2.5 System parameters…………………………………… 20 2.3 Experimental Results………………………………………… 21 2.3.1 Measurement Results………………………………... 21 2.4 Conclusion……………………….…….…….…….……...…. 26 3. An On-Chip Oscillator With Comparator Delay Compensation………….…………………………………………… 27 3.1 Motivation…………………………………………………… 27 3.2 Circuit Architecture…………………………………….……. 28 3.2.1 Overview of the Operation…………………….…….. 28 3.2.2 Proposed Oscillator………………………………….. 30 3.2.3 Current DAC…………………...……………………. 36 3.2.4 Simulation Results...………………………………… 37 3.3 Experimental Results………………………………………… 39 3.3.1 Measurement Results………………………………... 39 3.4 Conclusion……………………….…….…….…….……...…. 43 4. Conclusion and Future Work……………………………………… 44 4.1 Conclusion…………………………………………………… 44 4.2 Future Work…………………………………………………. 45 Bibliography ……………………………………………………………… 46 | |
| dc.language.iso | en | |
| dc.title | 具數位補償之低溫度係數弛張振盪器 | zh_TW |
| dc.title | Low TC Relaxation Oscillators with Digital Compensation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),魏嘉玲(Chia-Ling Wei),陳柏宏(Po-Hung Chen) | |
| dc.subject.keyword | 數位補償; 持張振盪器 | zh_TW |
| dc.subject.keyword | Digital compensation; relaxation oscillator | en |
| dc.relation.page | 48 | |
| dc.identifier.doi | 10.6342/NTU201801737 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2018-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-106-1.pdf 未授權公開取用 | 3.2 MB | Adobe PDF |
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