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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平 | |
dc.contributor.author | Chia-Hsien Wu | en |
dc.contributor.author | 吳家賢 | zh_TW |
dc.date.accessioned | 2021-06-08T02:14:38Z | - |
dc.date.copyright | 2016-02-02 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-12-10 | |
dc.identifier.citation | [1] Makoto Sugihara, “Recent Advances in Nanofabrication Techniques and Applications,” Intech, 2011, ch.4.
[2] Wai-Kei Mak; Chu, C., “E-beam lithography character and stencil co-optimization,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 33, no. 5, pp. 741–751, May 2014. [3] Chris A. Mack, “Lithographic Simulation: A Review,” in Proc. SPIE 4440 Lithographic and Micro-machining Techniques for Optical Component Fabrication, Vol. 4440, No. 59, pp. 53-72, 2001, Nov. 2001. [4] Peng Du; Wenbo Zhao; Shih-Hung Weng; Chung-Kuan Cheng; Graham, R., “Character design and stamp algorithms for character projection electron-beam lithography,” Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012, pp. 725-730. [5] Chin-Khai Tang; Ming-Shing Su; and Yi-Chang Lu, “LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems,” IEEE Signal Processing Letters, Vol. 20, No. 7, pp. 645-648, July 2013. [6] Stefan Landis, “Lithography,” 1st Edition. Amazon Digital Services, Inc., 2013, ch.3. [7] A. Fujimur, “Beyond light: The growing importance of E-beam,” Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. , Nov. 2009. [8] A. Fujimur, “Design for E-beam: Getting the best wafers without the exploding mask costs,” in Proc. Int. Symp. Quality Electron. Des., Mar. 2010. [9] A. Fujimura; T. Mitsuhashi, K. Yoshida; S. Matsushita; L. L. Chau; T. D. T. Nguyen; D. MacMillen, “Stencil design and method for improving character density for cell projection charged particle beam lithography,” U.S. Patent 20090325085, Jan. 2010. [10] Kiichi Sakamoto; Aki Fujimura. Making E-beam direct write faster. Available: http://electroiq.com/blog/2009/11/making-e-beam_direct/ [11] Fujimura, Aki, “Design for e-beam: design insights for direct-write maskless lithography” Proc. SPIE 7823, Photomask Technology 2010, Vol. 7823, Sep. 2010. [12] Pan, D.Z.; Jhih-Rong Gao; Bei Yu, “VLSI CAD for emerging nanolithography” VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on, 2012, pp. 1-4. [13] Yamada, A. and Yabe, T., 'Variable cell projection as an advance in electron-beam cell projection system,' Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures, Vol. 22, no. 6, pp. 2917-2922, 2004. [14] Akio Yamada. Advantest’s EBDW System; MCC System with CP. Available: http://www.sematech.org/meetings/archives/litho/7482/04-ADVANTEST%20Technology.pdf [15] ISCAS89 benchmark circuits provided by North Carolina State University https://filebox.ece.vt.edu/~mhsiao/iscas89.html [16] Takashi Maruyama; Yasuhide Machida; Shinji Sugatani; Hiroshi Takita; Hiromi Hoshino; Toshio Hino; Masaru Ito; Akio Yamada; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada, “CP element based design for 14nm node EBDW high volume manufacturing.” Proc. SPIE 8323, Alternative Lithographic Technologies IV, vol. 8323, March 2012. [17] Ikeno, R.; Maruyama, T.; Lizuka, T; Komatsu, S.; Ikeda, M.; Asada, K., “High-throughput electron beam direct writing of via layers by character projection using character sets based on one-dimensional via arrays with area-efficient stencil design,” Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, 2013, pp. 255-260. [18] Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada, “A Structured Routing Architecture and its Design Methodology Suitable for High-throughput Electron Beam Direct Writing with Character Projection,” International Symposium on Physical Design, 2013, pp.69-76. [19] Kun Yuan; Bei Yu; Pan, D.Z., “E-beam lithography stencil planning and optimization with overlapped characters,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 31, no. 2, pp. 167–179, 2012. [20] S. Manakli; H. Komami; M. Takizawa; T. Mitsuhashi; L. Pain, 'Cell projection use in mask-less lithography for 45 nm and 32-nm logic nodes,' Proc. SPIE 7271, Alternative Lithographic Technologies, vol. 7271, March 2009. [21] Yoichi Tomo; Koji Matsuoka; Yoshinori Kojima; Akira Yoshida; Isao Shimizu; Masaki Yamabe, ”Resolution limit in character projection e-beam system,” Proc. SPIE 3997, Emerging Lithographic Technologies IV, Vol. 3997, July 2000. [22] Chu, C.; Wai-Kei Mak, “Flexible packed stencil design with multiple shaping apertures for e-beam lithography,” Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, 2014, pp. 137-142. [23] Takashi Maruyama; Yasuhide Machida; Shinji Sugatani; Hiroshi Takita; Hiromi Hoshino; Toshio Hino; Masaru Ito; Akio Yamada; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada, “CP element based design for 14nm node EBDW high volume manufacturing,” Proc. SPIE 8323, Alternative Lithographic Technologies IV, Vol. 8323, April 2012. [24] Liu, I.; Fang, S.; Chang, Y., “Stitch-Aware Routing for Multiple E-Beam Lithography,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 34, no. 3, pp. 471-482, 2015. [25] Chin-Khai Tang; Ming-Shing Su; Yi-Chang Lu, “LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems,” IEEE Signal Processing Letters, Vol. 20, No. 7, July 2013. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19708 | - |
dc.description.abstract | 電子束曝光是一種使用電子束在晶圓表面上製造圖樣的方式,是光刻技術的延伸應用,電子束曝光的精度可以達到次10奈米量級,因此是一個非常具有潛力的曝光方式,在半導體工業中被廣泛使用於研究下一代超大型積體電路之曝光製造。然而電子束曝光最大的競爭弱勢就是產能的速度相對於193nm之製程太慢,無法提供目前半導體廠大量且快速生產的需求。
可變式形狀電子束技術利用可變的矩形實現所需的曝光圖案,目前超大型積體電路設計在等同面積下電晶體數量越來越多,且電路設計越來越複雜,可變式形狀電子束技術得需要大量的曝光次數,導致產率不良。單元投影式電子束由於一次曝光即可製作較大的圖案,故產能可大大提升。 因此,在這篇論文中,我們將提出單元投影式電子束的方法,包括電路布局圖的正規化、單元設計以及電路布局圖的投影演算法。我們主要致力於產能的提升。 最後,實驗數據顯示出我們的演算法在最重要的產能部份,優於先前所發表的演算法2.1倍以上,另外我們定了更多的限制維持住原本的電路功能。 | zh_TW |
dc.description.abstract | In recent decades, electron-beam lithography (EBL) is one of the strong candidates to draw custom shapes on the surface of wafer covered with electron-sensitive film called resist. The primary advantage of EBL is that it can draw custom patterns in sub-10nm resolution since the electron beam can change the solubility of the resist. Nevertheless, the low throughput of EBL is limiting its capability to mass production.
Variable Shaped Beam (VSB), one of the EBL technologies, exploits a set of variant rectangles to construct the layout. As the VLSI circuit design getting larger and more complicated, it takes more numbers of shots of VSB to realize modern design layouts. Thus, the bottleneck which limits the application of EBL system is the manufacturing feasibility. One approach to improve the throughput of VSB is the Character Projection (CP) techniques which constructs the layout with pre-designed characters for reducing the number of shots. In this thesis, we will introduce a series of methods, including character design, layout normalization and layout matching for improving the throughput of Character Projection (CP) Electron-Beam Lithography. According to the experimental results, our throughput is 2.1 times faster than the previously published algorithm. Besides, we set more conditions to ensure the circuit function unchanged. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T02:14:38Z (GMT). No. of bitstreams: 1 ntu-104-R02943094-1.pdf: 3128121 bytes, checksum: 6478f300e5b9825da98a131abe2dbe24 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 誌謝 ii
中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Lithography 2 1.2 Contributions 3 1.3 Organization 3 Chapter 2 Preliminaries 4 2.1 Maskless Lithography 4 2.2 Electron-beam Lithography 5 2.2.1 Gaussian Beam 6 2.2.2 Variable Shaped Beam 6 2.2.3 Character Projection 8 2.2.4 Variable Character Projection 9 2.3 Previous work 10 2.3.1 Problem Formula 10 2.3.2 Algorithms for variable character projection 12 Chapter 3 Character Design and Stamp Algorithms for 1D Wire Layout 16 3.1 Problem Formulation 17 3.1.1 Definitions 17 3.1.2 Assumptions 18 3.2 Framework of character projection 19 3.2.1 Layout normalization 20 3.2.2 Character design 27 3.2.3 Stamp Algorithm 34 Chapter 4 Experimental Results 46 4.1 Results of Normalization 49 4.2 Results of Throughput 51 Chapter 5 Conclusion and Future Work 56 REFERENCE 57 | |
dc.language.iso | en | |
dc.title | 針對投影式電子束微影技術之可調性單元設計暨投影演算法 | zh_TW |
dc.title | A Flexible Stamping Algorithm for E-Beam Projection Technology with the Designed Characters | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 方劭云,陳少傑,盧奕璋 | |
dc.subject.keyword | 電子束,曝光,投影,可變式形狀電子束技術,投影式曝光系統,電路布局,單元投影式電子束, | zh_TW |
dc.subject.keyword | Lithography,Electron Beam,Cell Projection,Character Projection,Variable Shaped Beam Technology, | en |
dc.relation.page | 60 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-12-11 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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ntu-104-1.pdf 目前未授權公開取用 | 3.05 MB | Adobe PDF |
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