具三維結構之瓦級並聯-並聯變壓器結合式CMOS功率放大器之研製

Abstract

隨著無線通訊系統的發展以及半導體製程的演進，以互補式金氧半場效電晶體實現射頻電路以成本優勢逐漸成為市場焦點，其中功率放大器為收發機中最關鍵的電路之一，本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。 論文的第二章描述了一個以90奈米互補式金氧半場效電晶體製程實現一個24-GHz的三個電晶體串接(堆疊式)功率放大器。為了增加單位面積輸出功率以及不犧牲電路可靠度，透過推疊數個電晶體提高供應電壓，並藉由實際模擬來選擇閘級的旁路電容以產生各電晶體適當的負載阻抗，最後透過推挽式的架構，在輸出及輸入端採用變壓器同時達到阻抗匹配、功率結合及單端與差動訊號轉換的功能。晶片面積為0.27 mm2，此電路達到輸出功率21.7dBm。 論文的第三章描述了一個以90奈米互補式金氧半場效電晶體製程實現一個三維結構之77-GHz變壓器功率結合式功率放大器，為了提高輸出功率，以放射狀的功率結合器和功率分配器實現八路功率結合，透過放射狀的功率結合器達到阻抗轉換的功能以降低輸出端匹配網路的阻抗轉換比，藉此降低因高阻抗轉換比造成的損耗，並將放射狀的功率結合器與分配器共用在電路的中央區域的面積，達到三維的結構來縮小因分配器與結合器所佔據的晶片面積，功率放大器的單元採用變壓器以同時達成功率結合、阻抗匹配以及單端與差動訊號的轉換。 論文的第四章描述了以橫向雙擴散金氧半場效電晶體實現一個5-GHz高輸出功率變壓器結合式放大器，透過並聯-並聯結合變壓器(PPCT)的技術，將多組變壓器實現在同一區域，降低在多路功率單元結合時，多個變壓器結合器所需要的面積，因此同時達到面積維持和一路變壓器一樣及多路的功率結合，並使用論文第三段所描述的放射狀三維架構，進一步將晶片面積縮小。

With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuit implemented in CMOS technology become the focal point in the industry with cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is on the design and analysis of power amplifier in CMOS. The chapter 2 describes a 24 GHz three series-connected (stacked) power amplifier implemented in 90 nm CMOS process. Increasing the supply voltage by stacking FETs to increase the power density per area without sacrificing reliability, and choosing the gate capacitance to generate the proper load impedance of each stacked-transistor by actual simulation. Adopting transformer in input and output terminals to achieve impedance matching, power combining and single to differential ended simultaneously in push-pull topology. The chip size is 0.27 mm2 and output power is 21.7 dBm. The chapter 3 describes a 77 GHz transformer combined power amplifier with 3-D architecture implemented in 90 nm CMOS process. The radial power combiner and splitter achieve the 8-ways power combination to increase output power. The radial power combiner with the function of impedance transformation reduces the impedance transformation ratio of output matching networks and alleviates the loss caused by large impedance transformation ratio. Sharing the center area of the chip to form a 3-D structure and thus the area occupied by the power combiner and power splitter can be reduced. The power cell adopts the transformer to realize power combining, impedance matching and single to differential ended simultaneously. The chapter 4 describes a 5 GHz high output power transformer combined power amplifier implemented in LDMOS process. By parallel-parallel combining transformer technique, the multiple transformers realize in the same area to reduce the area of multiple transformers in multi-way power combination. Thus it can maintain the area as 1-way transformer and function of multi-way power combination simultaneously. And using the 3-D radial architecture described in chapter 3 to further reduce the chip area.