高載子遷移率及穩定度改善之非晶相銦鎵鋅氧化物薄膜電晶體

Abstract

本論文對不同通道長度 (12微米 - 4微米)，但相同通道寬度及層間介電層長度之上閘極式非晶相銦鎵鋅氧化物(a-IGZO)薄膜電晶體之電性及穩定度進行了探討。發現隨著通道長度之縮減，a-IGZO電晶體之電性及穩定度有明顯的改善。此乃因層間介電層之成長採用高的矽甲烷(SiH4)流量，導致氫由層間介電層擴散至通道。因短通道電晶體之通道擁有較大比例之氫摻雜區域且已知氫摻雜進入a-IGZO可鈍化缺陷且貢獻自由電子，所以較短通道電晶體表現出較好之電性及穩定度。通道長度4微米之電晶體擁有高載子傳導率(26 cm2/V-s)及小的次臨界擺幅(155 mV/dec)和電磁滯效應(39 mV)。 對於元件穩定度測試，探討由於應力偏壓導致元件失真的原因及物理機制。對於正偏壓應力測試，電子被捕獲於閘極氧化層和shallow states內導致臨界電壓之正偏。反之對於負偏壓之應力測試，僅有少數之電洞被捕獲於閘極氧化層內導致臨界電壓些微之負偏。另外在照光負偏壓測試之後，臨界電壓因在通道中被離子化之deep states而負偏。 負偏壓穩定度測試通常會導致臨界電壓之負偏。 a-IGZO沉積之後以400 oC 熱退火之蝕刻阻擋層式(etching-stop layer type)電晶體在負偏壓穩定度測試後卻發現臨界電壓正偏之現象。此乃因熱退火環境下，鈉離子由鉬金屬之閘極摻雜進入閘極氧化層之影響。在負偏壓之下，鈉離子朝向閘極移動，鈉離子與閘極之間距離縮短，因此在鈉離子與閘極之間的壓降縮小導致相對應之臨界電壓正偏現象。於閘極及氧化矽層間插入氮化矽層，可抑制鈉離子移動，因此電晶體之臨界電壓於負偏壓應力測試之後表現正常負偏現象。

The electrical characterization and reliability of top-gate a-IGZO thin-film transistors (TFTs) with various channel length (12 m - 4 m) but fixed channel width and inter layer dielectric (ILD) length are discussed. As channel length decreases, the electrical properties and reliability are improved. This is due to the fact that the hydrogen atoms from ILD that are deposited with high SiH4 flow rate diffuse into the region at channel edge. Short channel devices have large proportion of high hydrogen incorporated region at channel edge. It is reported that the hydrogen incorporated in a-IGZO acts as donors and passivate defects. This leads that short channel devices show better performance. The devices with channel length of 4 m exhibit a high mobility of 26 cm2/V-s, a SS of 155 mV/dec and a hysteresis of 39 mV. The origins of instability of threshold voltage (VT) shift after reliability test are discussed. After positive bias stress (PBS), electrons are trapped into shallow states or trapped into gate insulator causing a positive VT shift. On the other hand, after negative bias stress (NBS), only a few inverted holes are trapped into gate insulator leading to a slightly negative VT shift. After the negative bias illumination stress (NBIS), ionized deep states in the channel resulted in a negative VT shift. The NBS normally yields a negative VT shift of the TFTs. However, a positive VT shift after NBS of the device with the post IGZO deposition annealing at 400 oC is observed in etching-stop layer type a-IGZO TFTs. The Na+ incorporation from Mo gate into the gate insulator after 400 oC annealing is responsible for this abnormal VT shift. The movement of Na+ ions toward the gate electrode by the negative gate bias decreases the distance between the gate electrode and the Na+ ions. Therefore, the voltage drop between the gate electrode and the Na+ ions reduces, and a corresponding positive VT shift is observed. Inserting a SiNx layer between the SiOx gate insulator and the Mo gate electrode can reduce the Na+ mobility, and thus resumes a normal negative VT shift.