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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Tse-Yi Hsieh | en |
| dc.contributor.author | 謝澤毅 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:41:17Z | - |
| dc.date.copyright | 2016-08-26 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-18 | |
| dc.identifier.citation | [1] Asad A.Abidi, “RF CMOS Comes of Age,” IEEE J. Solid-State Circuits, vol. 39, no. 4, Apr. 2004
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Keese, “An analysis and performance evaluation of a passive filter design techniques for charge pump PLL’s,” National Semiconductor application note 1001, July 2001. [9] 劉深淵, 鎖相迴路, 滄海書局, 2006. [10] Behzad Razavi, 類比積體電路設計, 李泰成, 滄海書局, 2010 [11] Ali Hajimiri, and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998. [12] Behzad Razavi, RF Microelectronics Second Edition, Los Angeles: Pearson, 2013. [13] D. B. Leeson, “A simple model of feedBack oscillator noise spectrum,” Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966. [14] C. Patrick Yue, and S. Simon Wang, “On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no.5, pp. 743-752, May 1998. [15] Pietro Andreani and Sven Mattisson, “On the use of MOS varactors in RF VCOs ,” IEEE J. of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000. [16] Pietro Andreani and Sven Mattisson, “On the use of MOS varactors in RF VCOs, ” IEEE J. of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000. [17] D. Zito and D. Pepe, 'Ku band LC-active 90nm CMOS VCO,' Active RF Devices, Circuits and Systems Seminar, Belfast, 2011, pp. 17-26. [18] Yiping Han, L. E. Larson and D. Y. C. Lie, 'A low-voltage 12GHz VCO in 0.13/spl mu/m CMOS for OFDM applications,' Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, CA, 2006, pp. 4 pp.-. [19] P. K. Tsai, T. H. Huang and Y. S. Lin, 'Integration of CMOS VCO and Frequency Divider for Ku-Band Low-Power Frequency Synthesizer,' Innovative Computing Information and Control, 2008. ICICIC '08. 3rd International Conference on, Dalian, Liaoning, 2008, pp. 235-235. [20] T. K. K. Tsang and M. N. El-Gamal, 'A high figure of merit and area-efficient low-voltage (0.7-1 V) 12 GHz CMOS VCO,' Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE, 2003, pp. 89-92. [21] J.G Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, pp.1723-1732, Nov. 1996 [22] P. Philippe, S. Bardy, S. Wane, F. Moreau, E. Thomas, L. Praamsma, “A low power 9.75/10.6GHz PLL in SiGe BiCMOS for Ku-band satellite LNBs,” 41st European Microwave Conference, Manchester, Oct. 2011, pp. 1130-1133 [23] Cheng Zhang, M. Syrzycki, “A high performance NMOS-switch high swing cascode charge pump for phase-locked loops,“ IEEE 55th International Midwest Symposium on Circuits and Systems, Boise, Aug. 2012, pp. 554-557– [24] P. Payandehnia., H. Maghami, “High speed CML latch using active inductor in 0.18μm CMOS technology,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2011, pp. 1-4.– [25] J. Yuan, and C. Svensson, “High speed CMOS circuit technique,” IEEE J. of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989. [26] L.Dickstein,http://www.gigatronics.com/uploads/document/AN-GT140A- Introduction-to-Phase-Noise-in-Signal-Generators.pdf, pp.4. [27] H. Alsuraisry, C. H. Yim, J. H. Cheng, J. H. Tsai and T. W. Huang, 'A X-band frequency synthesizer for FMCW radar in 180-nm CMOS,' 2015 Asia-Pacific Microwave Conference (APMC), Nanjing, 2015, pp. 1-3. [28] J. Y. Lee, K. Kim, S. C. Lee, J. K. Kwon, J. Kim and S. H. Lee, 'A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications,' 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, HI, 2007, pp. 233-236. [29] J. H. Tsai, C. H. Chao and H. D. Shih, 'A X-band fully integrated CMOS frequency synthesizer,' 2012 Asia Pacific Microwave Conference Proceedings, Kaohsiung, 2012, pp. 1226-1228. [30] T. H. Lin and Y. J. Lai, 'An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,' in IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 340-349, Feb. 2007. [31] J. H. Tsai, C. Y. Hsu and C. H. Chao, 'An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-??m CMOS technology,' Microwave Integrated Circuits Conference (EuMIC), 2015 10th European, Paris, 2015, pp. 238-241. [32] 趙家祥,”X頻帶9.75/10.6GHz頻率合成器的設計與實現”國立臺灣師範大學應用電子科技學系研究碩士論文,民國103年 [33] 黃紹緯,”使用0.18μm互補式金氧半製程之鎖相迴路與頻率合成器之設計與實現”國立臺灣師範大學應用電子科技學系研究碩士論文,民國103年 [34] 林建安,”寬頻鏡像抑制降頻混波器之研製以及頻率合成器在汽車防撞雷達和SATAIII的應用”國立臺灣大學電信工程學研究所碩士論文,民國103年 [35] 嚴俊軒,”低功耗K-Band變壓器回授振盪器及應用於X-Band雷達頻率調製連續波產生器之研究”國立臺灣大學電信工程學研究所碩士論文,民國103年 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18975 | - |
| dc.description.abstract | 近年來由於市場需求以及半導體製程的進步，無線通訊產業也越來越發達，隨著電路操作頻率不斷的提升，使得高頻積體電路的設計越來越重要。對於系統電路而言，不論是類比數位或是射頻應用，都需要一個乾淨的時脈產生器來提供穩定且精確的訊號源，使系統能維持更好的運作。本論文以射頻收發系統中所需的本地振盪器為應用範疇，實現了三個不同頻段的時脈產生電路，分別為低雜訊Ku-band電壓控制振盪器、X-band頻率合成器以及X-band雷達頻率調製連續波產生器。
第二章我們詳細介紹鎖相迴路內部架構和原理以及對鎖相迴路做迴路分析。 第三章實現了Ku-band的電壓控制振盪器，採用了NMOS交錯耦合對之LC共振式架構，為了降低輸出相位雜訊，在共振腔內加入了一個定電容，達到減少使用電感以提升整體共振腔的品質因素，為了避免負載效應引響操作頻率及電路特性，在振盪器的輸出端加入了共源極組態的緩衝放大器，並將汲極電阻以電感替換，減少電阻性的損耗以降低雜訊的引響。 第四章實現了X-band頻率合成器，採用了NMOS交錯耦合對電壓控制振盪器，以達到較低的功耗、較好的相位雜訊以及更大的輸出功率，整體迴路由電流模式邏輯(Current mode logic, CML)、真單相時脈(True single phase clock, TSPC)除頻器以及多模除頻器(Multi-modulus frequency divider, MMD)組合成除頻鏈，搭配靜態改良式相位頻率偵測器和只使用NMOS開關的充電泵配合迴路濾波器構成，在低功耗的條件下也有不錯的特性。 第五章設計了X-band雷達頻率調製連續波產生器，以第四章的X-band頻率合成器為基礎加入了三角積分調變器以及數位調變的控制，利用計數器的上下計數來切換三角積分調變器，以控制多模除頻器可以切換除數，使迴路在低通濾波器產生週期性的充放電以達到三角波的輸出。 | zh_TW |
| dc.description.abstract | In recent years, the wireless communications industries become more and more popular due to market demand. With the circuit operating frequency constantly upgrading, the high-frequency integrated circuit design is increasingly important. For system circuits, whether analog or digital RF applications, we need a clean clock generator to provide a stable and accurate signal source to improve the system performance. In this thesis, we achieve a clock generation circuit in three different frequency bands. A Ku-band low noise voltage controlled oscillator, an X-band frequency synthesizer and an X-band radar frequency modulated continuous wave generator, respectively.
In chapter 2 we detailed introduce the principles and analysis of phase-locked loop circuits. In chapter 3, a Ku-band voltage controlled oscillator has been designed and implemented. Using LC resonant architecture with the NMOS cross-coupled pair can reduce the output phase noise. To improve the overall resonator quality factor, an additional capacitance is added and the use of inductance can be deducted. In order to avoid the load effect affecting the operating frequency and the characteristics of circuit, a common source buffer amplifier is added and the drain resistors can be replaced by inductance to reduce the resistive loss and the noise of the circuit. In Chapter 4, an X-band frequency synthesizer has been designed and implemented. Using a LC voltage controlled oscillator with NMOS cross couple pairs to achieve low power consumption, good phase noise and greater output power. The whole divider chain circuit can be implemented by the current-mode logic frequency divider (CML), true single-phase clock (TSPC) frequency divider and a multi-mode frequency divider (MMD). The circuit is composed by phase frequency detector with modified static type, charge pump with only NMOS switches, third-order loop filter and the above VCO and divider chain. In addition, the circuit at low power conditions also has good characteristics. In Chapter 5, an X-band radar frequency modulated continuous wave generator has been designed. Based on the X-band frequency synthesizer in Chapter 4, the delta-sigma modulator and digital modulation are added to generate FMCW performance. Using counter counts up and down to switch the delta-sigma modulator. The delta-sigma modulator can switch the division ratio of the multi-mode frequency divider, and the low-pass filter can generate a periodic charge and discharge in order to achieve a triangular wave output. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:41:17Z (GMT). No. of bitstreams: 1 ntu-105-R03942012-1.pdf: 3988298 bytes, checksum: 2e0a3ee8845e8a2676c974a3eb9a31e3 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 口試委員會審定書 ii
誌謝 iii ABSTRACT v CONTENTS vii LIST OF FIGURES x LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 The Concept of the Phase-Locked Loop 3 2.1 Phase Frequency Detector, PFD 4 2.2 Charge Pump, CP 8 2.3 Low Pass Filter, LPF 16 2.4 Frequency Divider, FD 17 2.5 Voltage Control Oscillator, VCO 18 2.6 Analysis of Phase-Locked Loop 19 2.6.1 Analysis of Phase-Locked Loop system 19 2.6.2 Analysis of spur 26 Chapter 3 Design and Implementation Ku-band Voltage Control Oscillator 28 3.1 The introduction of voltage control oscillator 29 3.1.1 Design emphasis of the voltage control oscillator 29 3.1.2 Barkhausen’ Criteria [10] 30 3.1.3 Ring Oscillator and LC Oscillator 31 3.2 Cross-Coupled Pair LC Oscillator Analysis 33 3.2.1 Barkhausen’s Criteria Analysis [12] 33 3.2.2 Negative resistance Analysis 34 3.3 Phase noise 36 3.3.1 Definition of Phase noise 36 3.3.2 Lesson's Model of phase noise model [13] 40 3.3.3 Influence of phase noise 42 3.4 Phase noise 43 3.4.1 Inductance 43 3.4.2 Varactor [15] 45 3.5 Ku-band Voltage Control Oscillator Architecture 47 3.5.1 Simulation of inductance 48 3.5.2 Simulation result of the Voltage Control Oscillator 50 3.6 Measurement result 53 3.7 Result and Discussion 57 Chapter 4 Design and Implementation of X-band Frequency Synthesizer 63 4.1 Introduction 63 4.2 Circuit architecture and specifications 64 4.3 Phase frequency detector [21] 65 4.4 Charge Pump [23] 68 4.5 Third order low pass filter 69 4.6 Voltage control oscillator 72 4.7 Divider chain 76 4.8 Current mode logic divider (CML) 76 4.9 True single phase clock divider (TSPC) 79 4.9.1 Traditional D Flip-Flop type frequency divider 79 4.9.2 True Single Phase Clock (TSPC) frequency divider 79 4.10 Multi-mode divider (MMD) 81 4.10.1 Pulse Swallow Divider 81 4.10.2 Programmable multi-mode frequency divider architecture 82 4.10.3 Design of Divide-by-2/3 Cell 85 4.11 Phase-Locked Loop simulation 87 4.11.1 Frequency synthesizer system simulation 87 4.12 Measurement 89 4.13 Result and Discussion 97 Chapter 5 Design and Implementation of X-band FMCW radar generator 100 5.1 Introduction 100 5.1.1 FMCW radar 101 5.1.2 Range and velocity resolution of the FMCW 102 5.2 Building block of FMCW radar generator 102 5.2.1 Delta sigma modulator 103 5.2.2 Modulation control logic 105 5.3 Loop bandwidth for FMCW radar generator 107 5.4 FMCW radar generator Simulation 108 5.5 Measurement 109 5.6 Result and Discussion 112 Chapter 6 Conclusion 113 REFERENCE 115 | |
| dc.language.iso | en | |
| dc.title | 應用於無線通訊之Ku頻帶電壓控制振盪器及X頻帶頻率合成器之設計與實現 | zh_TW |
| dc.title | Design and Implementation of Ku-band Voltage Control Oscillator and X-band frequency synthesizer for wireless communication | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰(Jen-Han Tsai),邱煥凱(Hwann-Kaeo Chiou) | |
| dc.subject.keyword | 鎖相迴路,頻率合成器,電壓控制振盪器,FMCW,X-band, | zh_TW |
| dc.subject.keyword | Phase-Locked Loop,Frequency Synthesizer,Cross couple pair VCO,FMCW,X-band, | en |
| dc.relation.page | 118 | |
| dc.identifier.doi | 10.6342/NTU201603266 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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