鍺平面式與環繞式閘極場效應電晶體之研究

Abstract

在本篇論文中，主要著重在高遷移率鍺平面式與環繞式閘極場效應電晶體之製備與分析，並探討其氧化層介面特性、載子遷移率、應力響應以及相關製程整合。 在電晶體尺寸微縮進入10奈米節點後，使用高遷移率的通道材料來增加驅動電流，如:鍺以及III-V族合金材料，以及新穎的三維電晶體結構來改善短通道效應，如:鰭式、三閘極與環繞式閘極電晶體，都是未來半導體的重要發展方向。 在本論文中，我們利用二氧化鍺來鈍化鍺表面，發展出能達到低介面缺陷密度的鍺金氧半元件。我們也利用低溫電導法來探討其介面缺陷密度的分布，其介面缺陷密度可低至1E11 cm-2eV-1，且其金氧半電容特性曲線不會因頻率而改變，更進一步驗證二氧化鍺的鈍化效果。此外，在降低源極和汲極電阻方面，我們採用離子佈植來摻雜雜質，並利用兩階段的退火來活化接面，所製備之n+/p二極體具有高達1E5之開關電流比，以及接近1的理想因子。 在整合二氧化鍺鈍化技術、兩階段的源極/汲極活化、高介電常數介電層以及閘極後製程，我們已在鍺 (001) 和(111)基板上製作出高遷移率達~1050 cm2/V-s 以及 ~2200 cm2/V-s之n型電晶體。其在低電場下的高遷移率可歸功於低介面缺陷密度，使得庫侖散射效應大幅地降低。由於鍺元件有比矽還要嚴重的表面粗糙散射效應，導致其在高電場下的遷移率發生快速下降的現象，故有效降低表面粗糙度，其特性將能更加改善。最後，我們也探討鍺元件的應力響應，在(001)基板施加平行<110>方向的伸張應力約0.08%後，其最佳遷移率增益可達12%，如此一來元件的驅動電流也可以再進一步地提升。我們也利用模擬並以實驗確認 (001)基板遷移率增益較(111)為大，其原因可歸類為能帶分裂和電子重新分布至較小傳導質量的能谷。 我們也將高遷移率鍺通道與環繞式閘極場效應電晶體整合在絕緣層上矽基板上，並利用新的無接面電晶體操作模式，將電晶體性能大幅提升，例如:高電流開關比以及低次臨界擺幅。我們使用鍺磊晶配合內摻雜技術來避免離子佈植可能造成的晶格損壞，並且利用非等向性蝕刻來去除因為矽與鍺晶格不匹配所產生的差排缺陷。由於環繞式閘極有較好的閘極控制能力，能有效地控制通道中的壓降，並幫助無接面元件的通道達到完全空乏，我們在通道濃度為5E18 cm-3的元件上達到高電流開關比2E6以及低次臨界擺幅95 mV/dec。更甚者，我們也將元件微縮至9奈米以及將通道濃度提高到8E19 cm-3，其電流可高達390 uA/um。我們也發現在高電壓以及高溫操作下，無接面電晶體可提供比傳統反轉式電晶體更高的通道遷移率，主要是由於遷移率受制於庫倫散射，並對表面粗糙散射有較好的免疫力。 最後，我們也將探討極紫外光對高遷移率鍺元件的可靠度研究，傳統浸潤式微影技術在半導體製程邁入14~16奈米節點後將面臨物理波長的極限，極紫外光微影技術已被認為可提供更好的解析度，但由於其光子能量 (92 eV)太高，將會對元件產生光致衰退的現象。我們發現在經過極紫外光的照射後，元件在臨界電壓、次臨界擺幅、以及載子遷移率都發生衰退現象，主要原因是鍺與二氧化鍺表面以及二氧化鍺氧化層中產生斷鍵，進而使表面缺陷密度以及氧化層中的缺陷增加。同時表面缺陷密度的增加也導致庫侖散射效應加強，所以載子遷移率在低電場有顯著地下降。由於鍺的表面缺陷主要都靠近其傳導帶，所以p型電晶體對極紫外光有較好的免疫力。

In this dissertation, the fabrication and electrical characterization of germanium-based (Ge-based) planar and gate-all-around (GAA) field-effect-transistors (FETs) in terms of interface engineering, process integration, mobility characterization, and strain response are investigated. For the technology nodes of 10 nm and beyond, the high mobility channels (Ge, and III-V) are required to enhance drive current, and new device architectures (FinFET, tri-gates, and GAA FETs) are desired to reduce power and short channel effect. Since the Ge epichannel directly on Si can be a low-cost solution, Ge attracts the most interesting for emergent device integration. In the first part of this dissertation, the interface quality is effectively improved by passivating Ge surface with GeO2 using the rapid thermal oxidation. The dispersion-free C-V curves and Dit as low as ~1E11 cm-2eV-1 near the midgap are demonstrated. High on/off ratio n+/p diodes was fabricated by ion-implantation and activated by two-step annealing. The low defects within the junction are ensured with the near-unity ideality factor and high on/off ratio of 1E5. In the second part of this dissertation, with GeO2 passivation, and gate-last integration with high-k/metal gate, n-MOSFETs exhibiting high electron mobility for (001) and (111) Ge substrate and excellent transistor behaviors are fabricated. The peak electron mobilities that exceed the Si universal are ~1050 cm2/V-s and ~2200 cm2/V-s for (100) and (111) Ge n-MOSFETs, respectively. The interface trap density is effectively reduced down to ~1E11 cm-2ev-1 near midgap by GeO2 passivation, resulting in high peak mobility at low electric field. The fast roll-off of the mobility at high electric field is due to the large surface roughness scattering. By applying uniaxial <110> tensile strain of 0.08% on <110> channel direction, the best mobility enhancement of 12% can be achieved for (100) Ge n-MOSFETs. The larger mobility enhancement for the uniaxial tensile strain along <110> channel direction on (001) substrates is due to the larger reduction of conductivity mass as compared to (111) substrates. Next, the high performance junctionless Ge GAA p-FETs with the favorable on/off ratio and SS are fabricated and characterized. The in-situ boron doped epi-Ge on SOI is used to fabricate the JL GAA pFETs. The defect-free Ge fin was formed by anisotropic etching to etch away the high defective Ge near Ge/Si interface. The improved SS of 95 mV/dec, and the on/off ratio of 2E6 are achieved for the JL GAA device with the channel doping of 5E18 cm-3, and the fin width of 27 nm. The drain current at VGS - VT = VDS = -2 V can reach 390 uA/um for the device with the Nch of 8E19 cm-3 and the Wfin of 9 nm. The junctionless devices show higher mobility in the large (VGS - VT) region than the inversion devices due to less dependence on surface roughness scattering. Junctionless devices also show the increasing drive current at increasing temperature due to the nature of impurity scattering. Finally, high energy extremely-ultraviolet (EUV) induced Ge MOSFETs degradation is investigated. The energy of EUV (~92 eV) is much higher than the bonding energies for all materials used in Ge FETs, the bonds can be broken under irradiation. The degradation of threshold voltage, subthreshold swing, and channel mobility is attributed to the generation of interface traps and oxide fixed charges. Much more severe degradation of SS and VT on n-MOSFETs as compared to p-MOSFETs suggests that more interface defects in the upper half of Ge bandgap are generated by EUV radiation than lower half bandgap. The increase of interface trap is responsible for the mobility degradation of n-MOSFETs due to Coulomb scattering.