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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵 | |
dc.contributor.author | Yuan-Fu Lin | en |
dc.contributor.author | 林元莆 | zh_TW |
dc.date.accessioned | 2021-06-08T01:09:53Z | - |
dc.date.copyright | 2014-08-21 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-18 | |
dc.identifier.citation | [1] J. W. Jung and B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 684-697, Mar. 2013.
[2] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006 [3] S. Shahramian, et. al., “A pattern-guided adaptive equalizer in 65nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 354-355. [4] Y. M. Ying and S. I. Liu, “A 20Gb/s digitally adaptive equalizer/DFE with blind sampling,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 444-445. [5] W. S. Kim, C. K. seong, and W. Y. Choi, “A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 358-359. [6] Z. Deng, and A. M. Niknejad, “The speed–power trade-off in the design of CMOS true-single-phase-clock dividers,” IEEE J. Solid-State Circuits, vol. 45, no.11, pp. 2457-2465, Nov. 2010. [7] R. Inti, et. al., “A 0.5–2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance,” IEEE J. Solid-State Circuits, vol. 46, no.12, pp. 3150-3162, Dec. 2011. [8] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2003. [9] A. Agrawal et al., “A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220-3231, Dec. 2012. [10] J. W. Jung and B. Razavi, “A 25-Gb/s 5.8mW CMOS equalizer,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 44-46. [11] C. S. H. Wong et al., “A 50 MHz eight-tap adaptive equalizer for partial-response channels,” IEEE J. Solid-State Circuits, vol. 30, no. 6, pp. 228-234, Mar. 1995. [12] J. F. Bulzacchelli et al., “A 28 Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32 nm SOI CMOS technology,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 324-325. [13] K. Jung et al., “A 0.94 mW/Gb/s 22 Gb/s 2-tap partial-response DFE receiver in 40 nm LP CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 42-43. [14] K. Kaviani et al., “A 27 Gb/s 0.41-mW/Gb/s 1-Tap predictive decision feedback equalizer in 40-nm low-power CMOS,” IEEE Custom Integrated Circuit Conf. (CICC), Sep 2012. [15] J. E. Proesel and T. O. Dickson, “A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS,” IEEE Symp. VLSI Circuits, Jun 2011, pp. 206-207. [16] A. Emami-Neyestanak et al., “A 6.0 mW, 10.0 Gb/s receiver with switched-capacitor summation DFE,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 889-896, Apr. 2007. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18526 | - |
dc.description.abstract | 近幾年來,除了資料傳輸速度的高速成長之外,廣範圍的資料也被要求於各種多媒體和攜帶式裝置的應用。隨著傳輸速度的提升,許多嚴重的問題也浮現出來,相對於資料傳輸的速度,傳輸通道的有限頻寬就是其中一個問題,這個問題會使得原本傳送的訊號失真,導致嚴重的符際干擾並且使位元錯誤率升高。為了解決符際干擾問題,等化器被廣泛的運用來解決此問題。然而,傳輸通道的長度以及材質通常會隨著應用而不同。因此,在最近的通訊系統中,等化器也通常會伴隨著一個可適性的演算法。而在廣範圍的資料傳輸中,功率的效率的議題也開始被重視。
本論文最主要分成兩個部分。第二章提出一個介紹一個具有功率可調性的可適性線性等化器。在比較低的資料傳輸時,功率可調性可以提升功率效率。我們也提出一個利用計算訊號轉換次數的可適性演算法。此電路實作於40-nm CMOS製程。 第三章是介紹一個利用電荷導向式邏輯電路組成的決策回授等化器。為了降低系統的功率消耗,我們的設計使用了電荷導向式邏輯電路。並且利用SSLMS演算法來自動調整決策回授等化器的補償係數。此電路實作於40-nm CMOS製程。 | zh_TW |
dc.description.abstract | In recent years, in addition to the fast growing in data rate, wide-range data is also required in the applications of various multimedias and portable devices. As the data rate keeps rising, many significant problems appear. One is that the bandwidth is limited compared to the data rate. It will result a significant inter symbol interference (ISI) to degrade the bit error rate (BER). In order to deal with ISI, equalizers are widely adopted. However, the length or the material of the communication channel may be different depending on the application. Therefore, an adaptive algorithm with the equalizer is more popular in recent communication systems. In wide-range data rate application, power efficiency issue is also concerned.
This thesis is mainly divided into two parts. In Chapter 2, a 5-20 Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) architecture is proposed. We use a power scalable technique to improve the power efficiency for slow data rate. We also propose an adaptive algorithm using edge counting. This circuit is implemented in 40-nm CMOS process. A 5-20 Gb/s adaptive charge-steering decision-feedback equalizer (DFE) is presented in chapter 3. To lower power consumption of the system, charge-steering logic circuit is adopted in this design. We use sign-sign least mean square (SSLMS) algorithm to adjust the DFE’s taps adaptively. This circuit is implemented in 40-nm CMOS process. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:09:53Z (GMT). No. of bitstreams: 1 ntu-103-R01943047-1.pdf: 3241534 bytes, checksum: 59deecaf206fbc1af23ef354b4d15359 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Overview 2 1.2 Wireline Communication 2 1.3 High-Speed Circuits 3 1.3.1 Current-Mode Logic 3 1.3.2 Charge-Steering Logic 3 Chapter 2 A 5-20 Gb/s Power Scalable Adaptive Linear Equalizer Using Edge Counting 2 2.1 Motivation 6 2.2 Circuit Architecture 7 2.2.1 Circuit Description 7 2.2.2 Data Rate Detection 7 2.2.3 Calibrating CML/CMOS Converter 9 2.2.4 Equalization 9 2.3 Circuit Description 12 2.3.1 Analysis of Power Scalable CML Cell 12 2.3.2 CTLE and CMFB 13 2.3.3 CML/CMOS Converter 14 2.3.4 Pulse Generator 15 2.4 Experimental Results 17 2.4.1 Measurement Results 17 2.4.2 Die Photo and Performance Summary 23 Chapter 3 A 5-20 Gb/s Adaptive Charge-Steering DFE 25 3.1 Motivation 25 3.2 Circuit Description 28 3.2.1 Architecture Description 28 3.2.2 CTLE and DMUX 28 3.2.3 Quarter Rate DFE 29 3.2.4 CMFB 31 3.2.5 SSLMS Engine 34 3.4 Measurement Setup and Experimental Results 37 3.4.1 Measurement setup 37 3.4.2 Experimental Results 37 3.4.3 Die Photo and Performance Summary 40 Chapter 4 Conclusion and Future Work 43 4.1 Conclusion 43 4.2 Future Work 44 Bibliography 45 | |
dc.language.iso | zh-TW | |
dc.title | 50~200億位元之可適性線性等化器及決策回授等化器 | zh_TW |
dc.title | 5~20 Gb/s Adaptive Linear Equalizer and Decision-Feedback Equalizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢,汪重光,李俊毅 | |
dc.subject.keyword | 線性等化器,決策回授等化器,低功率,可適性, | zh_TW |
dc.subject.keyword | continuous time linear equalizer,decision feedback equalizer,low power,adaptive, | en |
dc.relation.page | 46 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2014-08-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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