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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 蔡坤諭(Kuen-Yu Tsai) | |
| dc.contributor.author | Hao-Yun Yu | en |
| dc.contributor.author | 余浩澐 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:07:41Z | - |
| dc.date.copyright | 2014-09-05 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-08-19 | |
| dc.identifier.citation | [1] '2011 tables of Lithography,' in ITRS, 2011th Ed., 2011.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18486 | - |
| dc.description.abstract | Line edge roughness (LER) influencing the electrical performance of circuit components is a key challenge for electron-beam lithography (EBL) due to the continuous scaling of technology feature sizes. Controlling LER within an acceptable tolerance that satisfies International Technology Roadmap for Semiconductors requirements while achieving high throughput become a challenging issue. Although lower dosage and more-sensitive resist can be used to improve throughput, they would result in serious LER-related problems because of increasing relative fluctuation in the incident positions of electrons. Directed self-assembly (DSA) is a promising technique to relax LER-related pattern fidelity (PF) requirements because of its self-healing ability, which may benefit throughput. To quantify the potential of throughput improvement in EBL by introducing DSA for post healing, rigorous numerical methods are proposed to simultaneously maximize throughput by adjusting writing parameters of EBL systems subject to relaxed LER-related PF requirements. A fast, continuous model for parameter sweeping and a hybrid model for more accurate patterning prediction are employed for the patterning simulation. The tradeoff between throughput and DSA self-healing ability is investigated. Preliminary results indicate that significant throughput improvements are achievable at certain process conditions. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:07:41Z (GMT). No. of bitstreams: 1 ntu-103-R01921065-1.pdf: 2646032 bytes, checksum: 6e7407eb9ebecf1ce25d52b3149f62e4 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iv STATEMENT OF CONTRIBUTIONS vii CONTENTS viii LIST OF FIGURES xi LIST OF TABLES xiv Chapter 1 Introduction 1 1.1 Moore’s law and lithography 2 1.2 Multiple-electron-beam–direct-write lithography 4 1.3 Direct self-assembly of block copolymers 7 1.4 Adjustment of electron-beam writing parameters 15 1.5 Organization of this thesis 16 Chapter 2 Patterning prediction in electron-beam lithography 18 2.1 Patterning prediction method 19 2.2 Patterning prediction with Monte Carlo algorithm 21 2.2.2 Estimation of the polar angle 23 2.2.3 Estimation of the azimuth angle 24 2.2.4 Estimation of the travel distance between two collisions 24 2.2.5 Estimation of the energy loss over electron travelling 24 2.2.6 Collision location determination 26 2.3 Energy distribution of electrons in resist 27 2.3.1 Point spread function 27 2.3.2 Accuracy improvement of NTU in-house Monte Carlo algorithm-based electron-scattering simulator with model parameters calibration 28 2.4 Computation effort reduction of Monte Carlo algorithm-based patterning prediction with proposed acceleration method 34 2.5 Patterning fidelity measurement 40 2.5.1 Line edge roughness 41 2.5.2 Gate critical dimension variation 43 Chapter 3 New e-beam writing parameters optimization method with patterning fidelity constraints relaxation 45 3.1 Optimization flow and settings 46 3.1.1 Fitting optimization functions of fmincon 48 3.2 Optimization flow and settings with region classification 50 Chapter 4 Application of the proposed writing parameters optimization method 55 4.1 Optimization settings and results for LER requirement relaxation 55 4.2 Optimization settings and results for LER and gate CD variation relaxation 59 4.3 Optimization settings and results for LER and gate CD variation relaxation with region classification 63 Chapter 5 Discussion of throughput improvement with direct self-assembly for pattern rectification 70 Chapter 6 Conclusions and future work 73 Appendix 75 Bibliography 76 Vita 84 Publication List 85 | |
| dc.language.iso | en | |
| dc.title | 利用圖形修復並藉由放寬之製像真確度條件以達到直寫微影之產能改善 | zh_TW |
| dc.title | Improvement in Direct-Write Lithography Throughput by Exploiting Relaxed Patterning Fidelity Requirements with Pattern Rectification | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳敏璋(Miin-Jang Chen),戴子安(Chi-An Dai),林本堅(Burn J. Lin),林浩雄(Hao-Hsiung Lin),李佳翰(Jia-Han Lee) | |
| dc.subject.keyword | 邊緣粗糙度,臨界尺寸,電子束微影,直寫,分子自組裝,產能,製像真確度, | zh_TW |
| dc.subject.keyword | line edge roughness,critical dimension,electron-beam lithography,direct-write,direct self-assembly,throughput,patterning fidelity, | en |
| dc.relation.page | 86 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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