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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李坤彥(Kung-Yen Lee) | |
| dc.contributor.author | Chen-Dong Tzou | en |
| dc.contributor.author | 鄒振東 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:05:28Z | - |
| dc.date.copyright | 2020-08-24 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-18 | |
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Ninomiya et al., 'Ultra-low on-resistance 60–100 V superjunction UMOSFETs fabricated by multiple ion-implantation,' in Proc. ISPSD, 2004, 177-180. [20] X. Zhong et al., 'Experimental Demonstration and Analysis of a 1.35-kV 0.92-mW · cm2 SiC Superjunction Schottky Diode,' IEEE Transactions on Electron Devices, vol. 65, 1458-1465, 2018. [21] J. Weiße et al., 'Vertical and Lateral 4H-SiC Charge Compensation Devices Fabricated by Energy Filter Ion Implantation,' in International Conference on Silicon Carbide and Related Materials, 2019. [22] mi2-factory, https://mi2-factory.com/. [23] A. Bolotnikov et al., 'SiC charge-balanced devices offering breakthrough performance surpassing the 1-D Ron versus BV limit,' in Materials Science Forum, 2019, 655-659. [24] S. Harada et al., 'First demonstration of dynamic characteristics for SiC superjunction MOSFET realized using multi-epitaxial growth method,' in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, 8.2. 1-8.2. 4. [25] T. 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Imam et al., 'Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices,' IEEE Transactions on Electron Devices, vol. 51, 141-148, 2004. [31] A. W. Ludikhuize, 'A review of RESURF technology,' in 12th International Symposium on Power Semiconductor Devices ICs. Proceedings (Cat. No. 00CH37094), 2000, 11-18. [32] H. Vaes et al., 'High voltage, high current lateral devices,' in 1980 International Electron Devices Meeting, 1980, 87-90. [33] R. Myers-Ward et al., 'Spontaneous Conversion of Basal Plane Dislocations in 4° Off-Axis 4H–SiC Epitaxial Layers,' Crystal growth design, vol. 14, 5331-5338, 2014. [34] T. Kimoto, 'Bulk and epitaxial growth of silicon carbide,' Progress in Crystal Growth and Characterization of Materials, vol. 62, 329-351, 2016. [35] 陈万军 et al., 'PSJ 高压器件的优化设计,' 半导体学报, vol. 27, 1089-1093, 2006. [36] W. Saito et al., 'Over 1000V semi-superjunction MOSFET with ultra-low on-resistance below the Si-limit,' in Proceedings. ISPSD'05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005., 2005, 27-30. [37] B. J. Baliga, 'Power semiconductor device figure of merit for high-frequency applications,' IEEE Electron Device Letters, vol. 10, 455-457, 1989. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18443 | - |
| dc.description.abstract | 超接面結構應用於矽基功率元件已經行之有年，其結構能夠有效地突破矽功率元件崩潰電壓與特徵導通電阻之權衡，大幅降低常規元件之特徵導通電阻。本論文致力於開發1200 V 4H-SiC超接面金氧半場效電晶體，前期使用Synopsys TCAD Sentaurus進行元件設計，利用電荷平衡的概念開發出兩種超接面結構，其一為分段式超接面結構，其能夠降低20%的特徵導通電阻，其二為半柱式超接面結構，其能夠降低18%的特徵導通電阻且多層磊晶次數也只需分段式超接面結構的一半次數即可達成。因此最後採用半柱式超接面結構予以實作。 SJ MOSFET製作完成後，本次實驗量測到的最佳元件其導通電阻為8.46 mΩ‧cm^2，崩潰電壓為1114 V，臨界電壓3.32 V，最高崩潰電壓可至1176 V。導通電阻過高主要是因為P-well 表面濃度太濃導致通道電阻上升。 | zh_TW |
| dc.description.abstract | A superjunction (SJ) structure has been used in the silicon-based power devices which could effectively break through the trade-off between breakdown voltage (BV) and the specific on resistance (Ron,sp). In this work, we are committed to developing 1200 V 4H-SiC SJ MOSFET. In the beginning, Synopsys TCAD Sentaurus was used for device structure simulation and then two SJ structures were developed based on the charge balance concept. One of them is the Separate pillar SJ (S-SJ) structure. It can reduce the Ron,sp by 20%, comparing with the conventional power MOSFET. The second is the half pillar SJ (HF-SJ) structure, which can reduce the Ron,sp by 18%. In addition, the number of multi-epi growth times of HF-SJ is half of that of S-SJ structure. Therefore, the HF-SJ structure was finally implemented. The best Ron,sp measured in this experiment is about 8.46 mΩ‧cm^2, and the BV is 1114 V and the threshold voltage is 3.32 V. The maximum BV could achieve 1176 V. The Ron,sp is much higher than expected mainly because the concentration of the P-well surface is too high and consequently makes the channel resistance higher. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:05:28Z (GMT). No. of bitstreams: 1 U0001-1208202015031600.pdf: 4659728 bytes, checksum: 86f7d462a9913525d4706ca7195afd62 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 致謝 II 中文摘要 III Abstract IV 目錄 V 圖目錄 VII 表目錄 XIII 第一章 緒論 1 1.1 前言 1 1.2 碳化矽介紹 2 1.3 研究動機 4 1.4 論文大綱 5 第二章 功率元件發展回顧 6 2.1 常見的功率元件種類簡介 6 2.2 垂直型雙佈植金氧半場效電晶體 7 2.2.1 垂直型雙佈植金氧半場效電晶體結構與製程 7 2.2.2 垂直型雙佈植金氧半場效電晶體順向導通機制 9 2.2.3 垂直型雙佈植金氧半場效電晶體逆向崩潰機制 13 2.2.4 碳化矽高功率元件的挑戰與市場應用 16 2.3 超接面的發展 19 2.3.1 超接面的結構及原理 19 2.3.2 超接面的製程方法 23 2.3.3 碳化矽超接面金氧半場效電晶體文獻回顧 27 2.4 邊緣終端區保護結構 31 2.4.1 邊緣終端結構理論 31 2.4.2 邊緣終端結構類型 32 第三章 模擬結果分析與討論 37 3.1 模擬軟體環境設定 37 3.1.1 模擬環境 37 3.1.2 模擬方法 38 3.2 元件主動區靜態特性 41 3.2.1 常規DMOSFET模擬設計 41 3.2.2 分段式SJ DMOSFET模擬設計 48 3.2.3 半柱式SJ DMOSFET模擬設計 55 第四章 半柱式SJ DMOSFET實驗量測結果與討論 62 4.1 元件順向操作特性分析 63 4.2 元件逆向崩潰電壓分析 67 第五章 結論與未來展望 70 5.1 結論 70 5.2 未來工作 71 參考文獻 72 | |
| dc.language.iso | zh-TW | |
| dc.title | 1200V 4H-SiC 超接面金氧半場效電晶體設計與製作 | zh_TW |
| dc.title | Design and Fabrication of 1200V 4H-SiC Superjunction MOSFET | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李佳翰(Jia-Han Li),黃智方(Chih-Fang Huang),胡振國(Jenn-Gwo Hwu) | |
| dc.subject.keyword | 4H-SiC,超接面,金氧半場效電晶體,電荷平衡,特徵導通電阻,崩潰電壓, | zh_TW |
| dc.subject.keyword | 4H-SiC,Superjunction,MOSFET,Charge Balance,Ron,sp,BV, | en |
| dc.relation.page | 74 | |
| dc.identifier.doi | 10.6342/NTU202003095 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-08-19 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 工程科學及海洋工程學研究所 | zh_TW |
| 顯示於系所單位： | 工程科學及海洋工程學系 | |
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