Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18381Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Chien-Lun Hsu | en |
| dc.contributor.author | 徐健倫 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:02:22Z | - |
| dc.date.copyright | 2014-10-03 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-10-02 | |
| dc.identifier.citation | [1] Shengxi Diao, Yuanjin Zheng, Yuan Gao, San-Jeow Cheng, Xiaojun Yuan, Minkyu Je, and Chun-Huat Heng, “A 50-Mb/s CMOS QPSK/O-QPSK Transmitter Employing Injection Locking for Direct Modulation,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, Jan. 2012.
[2] Federal Communications Commission, “Notice of Proposed Rulemaking,” pp. 4– 9, Mar., 2009 [3] Couch, L. “Digital and Analog Communication Systems,” Upper Saddle River, NJ: Prentice Hall, 2001. [4] S. Samadian, R. Hayashi, and A. A. Abidi, “Demodulators for a Zero-IF Bluetooth Receiver,” IEEE Journal of Solid State Circuits, vol. 38, no. 8, pp. 1393–1396, Aug. 2003. [5] D. Han and Y. Zheng, “An Ultra Low Power GFSK Demodulator for Wireless Body Area Network,” IEEE Proceedings Europe Solid-State Circuits Conference, pp. 434–437, Sept. 2008. [6] Y.-Hong Liu, A. Ba, J.H.C van den Heuvel, K. Philips, G. Dolmans, and H. de Groot, “A 1.2nJ/b 2.4GHz Receiver with a Sliding-IF Phase- to-Digital Converter for Wireless Personal/Body-Area Networks,” IEEE ISSCC Dig. Tech. Papers, pp.166–168, Feb. 2014. [7] P. Mak, S.-P. U, and R. P.Martins, “Transceiver Architecture Selection: Review, State-of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, 2007. [8] K. Koli, S. Kallioinen, J. Jussila, P. Sivonen, and A. Parssinen, “A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS,” IEEE Journal of Solid State Circuits, vol. 45, no. 12, pp. 2807–2818, Dec. 2010. [9] M. Sharifkhani, M. Sachdev, “A Phase-Domain Continuous-Time 2nd-Order Delta-Sigma Frequency Digitizer,” IEEE Custom Integrated Circuit Conf., pp. 205–208, Sept. 2006. [10] S.-J. Huang and Y.-Y Lin, “A 1.2V 2MHz BW 0.084mm2 CT Delta Sigma ADC with -97.7dBc THD and 80dB DR Using Low-latency DEM,” IEEE ISSCC Dig. Tech. Papers, pp. 172–174, Feb. 2009. [11] M. Englund, K. B. Ostman, O. Viitala, M. Kaltiokallio, K. Stadius1, K. Koli, and J. Ryynanen, “A Programmable 0.7-to-2.7GHz Direct ΔΣ Receiver in 40nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp.470–472, Feb. 2014. [12] R. Schreier, The Delta-Sigma Toolbox for Matlab, Oregon State Univ. Corvallis, Nov. 1999. [13] A. Mirzaei, H. Darabi, J. C. Leete, X. Chen, K. Juan, and A. Yazdi, “Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct- Conversion Receivers,” IEEE Journal of Solid State Circuits, pp. 2678–2688, Oct. 2009. [14] M. C. M. Soer, E. A. M. Klumperink, P. de Boer, F. E. van Vliet, and B. Nauta, “Unified Frequency-Domain Analysis of Switched-Series-Passive Mixers and Samplers,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 57, no.10, pp. 2618–2631, Oct. 2010. [15] A. Mirzaei, and H. Darabi, “Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 58, no.5, pp. 879– 892, May 2011. [16] A. Ghaffari, E. A. M. Klumperink, M. C. M. Soer, and B. Nauta, “Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification,” IEEE Journal of Solid State Circuits, vol. 46, no. 5, pp. 998–1010, May 2011. [17] N. Kim, L. E. Larson, and V. Aparin,” A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA,” IEEE Journal of Solid State Circuits, vol. 44, no. 8, pp. 2126–2137, Aug. 2009. [18] S. Ouzounovl, R. van Veidhoven, C. Bastiaansen, K. Vongehrl, R. van Wegberg, G. Geelen, L. Breems, and A. van Roermund, “A 1.2V 121-Mode CT Delta-Sigma Modulator for Wireless Receiver in 90nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 242–243, Feb. 2007. [19] C. Andrews and A. C. Molnar, “Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers,” IEEE Transactions on Circuits and Systems-I, vol. 57, no. 12, pp.3092–3103, Dec. 2010 [20] N. Kim, V. Aparin, and L. E. Larson, “A resistively degenerated wide- band CMOS passive mixer with low noise figure and high IIP2,” IEEE Trans. Microwave Theory and Techniques, vol. 58, no. 4, pp.820–830, Apr. 2010. [21] M. Soer, E. Klumperink, B. Nauta, and F. van Vliet, “A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 1744– 1746, Feb. 2012. [22] R. Zanbaghi, P. Kumar Hanumolu, and T. S. Fiez,” An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT Modulator Dissipating 13.7-mW,” IEEE Journal of Solid State Circuits, vol. 48, no. 2, pp. 487–501, Feb. 2013. [23] Y.-H. Liu, C.-L. Li, and T.-H. Lin, “A 200-pJ/b MUX-Based RF Transmitter for Implantable Multichannel Neural Recording,” IEEE Trans. Microwave Theory and Techniques, vol. 57, no.10, pp. 2533–2541, Oct. 2009. [24] J. Pandey, J. Shi, and B. Otis, 'A 120 μW MICS/ISM-band FSK receiver with a 44 μW low-power mode based on injection-locking and 9x frequency multiplication,' IEEE ISSCC Dig. Tech. Papers, pp. 460–461, Feb. 2011. [25] S. Haykin, Communication Systems, 4th ed., New York: John Wiley, 2001. [26] D. Han and Y. Zheng, 'A Mixed-Signal GFSK Demodulator Based On Multithreshold Linear Phase Quantization,' IEEE Transactions on Circuits and Systems: II - Express Briefs, vol. 56, no. 9, pp. 719–723, Sept. 2009. [27] R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 3th ed., New Jersey: John Wiley, 2010. [28] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. [29] R.-Fu Ye, Tzyy-Sheng Horng, and Jian-Ming Wu, “Ultralow Power Injection- Locked GFSK Receiver for Short-Range Wireless Systems ,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 99, pp. 1–5, 2012. [30] B. E. Boser and B. A. Wooley, The Design of Sigma-Delta Modulation Analog-to-Digital Converters,” IEEE Journal of Solid State Circuits, vol. 23, no. 12, pp. 1298–1308, Dec. 1988. [31] R. Schreier and G. C. Temes, Understanding Delta-sigma Data Converters, Wiley-IEEE Press, 2004. [32] J. Yu and F. Maloberti, “A Low-Power Multi-Bit Delta-Sigma Modulator in 90-nm Digital CMOS without DEM,” IEEE Journal of Solid State Circuits, vol. 40, no. 12, pp. 2428–2436, Dec. 2005. [33] C.-H. Weng, C.-C. Lin, Y.-C. Chang, and T.-H. Lin, 'A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator with an Asynchronous Sequential Quantizer and Digital Excess Loop Delay Compensation,' IEEE Transactions on Circuits and Systems-II, vol. 58, pp. 867–871, Dec. 2011. [34] J. Bae, L. Yan, and H.-J. Yoo, “A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications,” IEEE Journal of Solid State Circuits, vol. 46, no. 4, pp. 928–937, Apr. 2011. [35] S. Ouzounov, et al., “A 1.2V 121-Mode CT Delta-Sigma Modulator for Wireless Receiver in 90nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 242–243, Feb. 2007. [36] R.Schreier, The Delta-Sigma Toolbox for Matlab, Oregon State Univ. Corvallis, Nov. 1999. [37] K. Koli, S. Kallioinen, J. Jussila, P. Sivonen, and A. Parssinen, “A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS,” IEEE Journal of Solid State Circuits, vol. 45, no. 12, pp. 2807–2818, Dec. 2010. [38] M. C. M. Soer, E. A. M. Klumperink, Z. Ru, F. E. van Vliet, and B. Nauta, “A 0.2-to-2.0GHz 65nm CMOS Receiver Without LNA Achieving >11dBm IIP3 and <6.5 dB NF,” IEEE ISSCC Dig. Tech. Papers, pp.222–224, Feb. 2009. [39] J. Masuch, Member, and M. Delgado-Restituto, “A 1.1-mW-RX -81.4-dBm Sensitivity CMOS Transceiver for Bluetooth Low Energy,” IEEE Trans. Microwave Theory and Techniques, vol. 61, no.4, pp. 1660–1673, Apr. 2013. [40] W. W. Si, D. Weber, S. Abdollahi-Alibeik, L. MeeLan, R. Chang, H. Dogan, G. Haitao, Y. Rajavi, S. Luschas, S. Ozgur, P. Husted, and M. Zargari, “A single-chip CMOS Bluetooth for v2.1 radio SoC,” IEEE ISSCC Dig. Tech. Papers, pp. 618–620, Feb. 2008. [41] C. P. Lee, A. Behzad, B. Marholev, V. Magoon, I. Bhatti, D. Li, S. Bothra, A. Afsahi, D. Ojo, R. Roufoogaran, T. Li, Y. Chang, K. R. Rao, S. Au, P. Seetharam, K. Carter, J. Rael, M. Macintosh, B. Lee, M. Rofougaran,R. Rofougaran, A. Hadji-Abdolhamid, M. Nariman, S. Khorram,S. Anand, E. Chien, S. Wu, C. Barrett, L. Zhang, A. Zolfaghari, H. Darabi, A. Sarfaraz, B. Ibrahim, M. Gonikberg, M. Forbes, C. Fraser, L. Gutierrez, Y. Gonikberg, M. Hafizi, S. Mak, J. Castaneda, K. Kim, Z. Liu, S. Bouras, K. Chien, V. Chandrasekhar, P. Chang, E. Li, and Z. Zhao, “A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier,” IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 454–455. [42] D. Han and Y. Zheng, 'A Mixed-Signal GFSK Demodulator Based on Multi-threshold Linear Phase Quantization,' IEEE Transactions on Circuits and Systems-II, vol. 56, no. 9, pp. 719–723, Sep. 2009. [43] H. Kaol, M. Yang, T. Lee, 'A delay-Line-Based GFSK Demodulator for Low-IF Receivers,' IEEE ISSCC Dig. Tech. Papers, pp. 88–90, Feb. 2007. [44] B. Xia, C. Xin, W. Sheng, A. Yakov Valero-Lopez, and E. Sanchez-Sinencio, “A GFSK Demodulator for Low-IF Bluetooth Receiver,” IEEE Journal of Solid State Circuits, vol. 38, no. 8, pp. 1397–1400, Aug. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18381 | - |
| dc.description.abstract | 近年來，隨著半導體製程的進步，近身通訊網路(WBAN 802.15.6)等短距離的無線通訊系統蓬勃發展。但是由於電池能量密度在近期並未有顯著的提升，尺寸上的限制，導致傳統的收發機架構無法直接應用在低功耗的攜帶式或植入式生醫設備。因此如何提升無線收發機的能量效率，是非常重要的議題。
本論文提出一個具高能量效率，操作在四億赫茲的無線射頻接收機。採用高斯頻率調變(GFSK)，頻率調變相對於其他調變方式具有較高的雜訊忍受能力。運作核心則是以鎖相迴路架構的特性解調輸入的頻率調變信號。此接收機架構是將射頻接收區塊及解調數位化區塊做結合，並利用連續時間三角積分技術取得較佳的信號雜訊比。因此，可簡化系統架構，進而降低成本及功耗。此接收機是使用台積電90奈米製程設計，消耗功率為3.32 毫瓦，當接收 2-Mbps 的訊號時，能源效益為1.66 nJ/bit，此接收器經由模擬得知其靈敏度為-76 dBm。 | zh_TW |
| dc.description.abstract | Recently, as the advancement of semiconductor, short range wireless applications like the wireless body area network (WBAN) experience a rapid growth. However, the improvement in battery energy density does not catch up with the semiconductor, traditional transceiver architecture cannot be implemented in low power portable or implantable bio-medical application. Therefore, there exists a critical issue of how to enhance the transceiver energy efficiency.
In this work, a 400-MHz GFSK receiver is present. The GFSK signals store the input information in its frequency and are much more robust against channel noise. This work adopted a PLL-based architecture which can track the input frequency to demodulate GFSK signal. The proposed receiver combines RF receiving block with demodulation digitizing block. To get better SNDR, it also adopts the technique of continuous-time delta-sigma modulation. Therefore, it reduces the cost and power consumption by simplifying system architecture. The receiver is fabricated in TSMC 90-nm CMOS technology. It consumes 3.32 mW with 1.2-V supply. The simulated system sensitivity is -76 dBm. The energy efficiency is 1.66 nJ/bit with 2-Mbps input signal. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:02:22Z (GMT). No. of bitstreams: 1 ntu-103-R00943006-1.pdf: 3798600 bytes, checksum: 56a3e4425ba8c6b4c8df953f930172e2 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Overview 3 Chapter 2 Receiver Architectures and Digital Modulation Schemes 4 2.1 Modulation Scheme 4 2.2 Conventional FSK Receiver Architectures 6 2.2.1 Zero-crossing detector 6 2.2.2 PLL based receiver [6] 8 2.3 Fundamental of Delta-Sigma Modulation (DSM) 9 Chapter 3 An Energy-efficient 2nd-Order Delta-Sigma Frequency Digitizer 13 3.1 Proposed GFSK Receiver Architecture 13 3.2 System Design 17 3.2.1 Link Budget Analysis 17 3.2.2 DSM System Analysis 19 Chapter 4 Circuit Implementations 25 4.1 Low Noise Amplifier 25 4.2 Passive Mixer 28 4.3 Loop Filter 33 4.4 Flash Quantizer 36 4.5 Digitally Controlled Ring Oscillator 39 4.6 Current-steering Digital-to-Analog Converter (DAC) 42 4.7 Overall System Simulation 43 Chapter 5 Measurement Setup and Experimental Results 47 5.1 Chip Layout 47 5.2 Measurement Results 47 5.2.1 Low Noise Amplifier 47 5.2.2 Digitally Controlled Ring Oscillator 49 5.2.3 Demodulation 51 Chapter 6 Conclusions and Future Works 55 6.1 Conclusions 55 6.2 Future Works 55 References 57 | |
| dc.language.iso | en | |
| dc.title | 具二階三角積分調變技術之頻率調變射頻接收機 | zh_TW |
| dc.title | Design of an Energy-efficient Frequency Digitizer Using 2nd-order Delta-Sigma Modulation Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曾英哲,林永裕,陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 高斯頻率鍵移接收機,高斯頻率鍵移解調器,低功耗頻率鍵移接收機, | zh_TW |
| dc.subject.keyword | low-power GFSK receiver,GFSK demodulator,frequency digitizer, | en |
| dc.relation.page | 62 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-10-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-103-1.pdf Restricted Access | 3.71 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.