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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | |
| dc.contributor.author | Yen-Hsin Wei | en |
| dc.contributor.author | 魏衍昕 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:01:27Z | - |
| dc.date.copyright | 2015-02-04 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-11-26 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18361 | - |
| dc.description.abstract | 本論文提出一個四通道十二位元連續漸進暫存類比數位轉換器，使用了提出的數位較正方式來補償時間偏移誤差，轉換器達到六億赫茲取樣頻率。多通道類比數位轉換器共使用了四個通道。數位混波使用來估計時間偏移量，再使用本論文所提出的延遲取樣雙核心方法來做時間偏移的校正。晶片用四十奈米CMOS製成製作，改善多通道寄生頻率音調從-50分貝到-76分貝，並且達到61.7分貝的訊號對雜訊與諧波比，功耗23毫瓦從一個0.9伏的供應電壓。品質因數(FoM)是38.7fJ/conversion-step，核心電路佔據0.3毫米平方面積。 | zh_TW |
| dc.description.abstract | A four channel time-interleaved 12-b SAR ADC, employing the proposed digital calibration technique to correct timing skew, achieves a 600-MHz sampling rate. The interleaved ADC composed of four channel SAR ADC. Digital mixing method is used to estimate timing skew, and proposed dual core with delay sampling is used to correct the timing skew. The ADC has been fabricated in a 40-nm CMOS technology, improves interleaving spurious tones from -50dB to -76dB and achieves a 61.7-dB SNDR while dissipating 23 mW from a 0.9-V power supply. The figure of merit (FoM) is 38.7 fJ/conversion-step and the active area is 0.3 mm2 | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:01:27Z (GMT). No. of bitstreams: 1 ntu-103-R01943021-1.pdf: 4455877 bytes, checksum: f11693692b1fa625c967a54bda20275b (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii Contents iv List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of ADCs 5 2.1 Introduction 5 2.2 ADC Performance Metrics 5 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 5 2.2.2 Signal-to-Noise Ratio (SNR) 8 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 9 2.2.4 Effective Number-of-Bits (ENOB) 10 2.2.5 Spurious-Free Dynamic Range (SFDR) 10 2.2.6 Figure of Merit (FoM) 11 2.3 Architectures of Analog-to-Digital Converters 11 2.3.1 Flash ADC 11 2.3.2 Subrange ADC 12 2.3.3 Successive Approximation ADC 13 2.3.4 Interleaved ADC 15 2.4 Error Sources in Interleaved ADCs 16 2.4.1 Offset Mismatch 17 2.4.2 Gain Mismatch 18 2.4.3 Phase Skew 19 Chapter 3 Calibration Scheme for Timing Mismatches 21 3.1 Introduction 21 3.2 Timing Skew Calibration 21 3.3 Digital Mixing Method 23 3.4 Proposed Digital Timing Skew Correction Scheme. 25 3.4.1 Principle 25 3.4.2 Circuit description 28 3.4.3 Skew Calibration Algorithm 30 3.5 Frequency Domain Analysis 34 3.6 Design Consideration 41 3.7 Behavior Simulation 43 3.8 Summary 44 Chapter 4 Circuit Implementation 45 4.1 Introduction 45 4.2 Bootstrapped switch 45 4.3 Comparator 46 4.4 Data register 48 4.5 Capacitive DAC 51 4.6 Clock Generator 57 4.7 Post-Layout Simulation 59 4.8 Channel Mismatch Correction 60 4.9 Summary 62 Chapter 5 Experimental Results 63 5.1 Introduction 63 5.2 Print Circuit Board Design 63 5.3 Measurement Setup 64 5.4 Measurement Results 65 5.4.1 12-bit 600MS/s Time-Interleaved ADC 65 5.4.2 Timing Skew Calibration 71 5.5 Summary 75 5.6 Conclusions 76 5.7 Future Works 76 Bibliography 77 | |
| dc.language.iso | zh-TW | |
| dc.title | 具背景時間偏移較正十二位元六億取樣頻率多通道類比數位轉換器 | zh_TW |
| dc.title | A 12-bit 600MS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,陳信樹,謝志成 | |
| dc.subject.keyword | 多通道類比數位轉換器,時間偏斜校正, | zh_TW |
| dc.subject.keyword | Time-Interleaved ADC,timing skew calibration, | en |
| dc.relation.page | 80 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-11-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-103-1.pdf 未授權公開取用 | 4.35 MB | Adobe PDF |
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