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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳怡然(Yi-Jan Chen) | |
dc.contributor.author | Wei-Hsin Teng | en |
dc.contributor.author | 滕偉新 | zh_TW |
dc.date.accessioned | 2021-06-08T01:01:05Z | - |
dc.date.copyright | 2015-08-11 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-12-02 | |
dc.identifier.citation | [1] Fabien Franc, “LED Power-Management Strategies for LCD Backlighting”, Electronic Design, Sep 1, 2006
[2] Marty Brown, “Switch mode Power Supply Reference Manual and Design Guide”, Application Note, ON Semiconductor, Apr. 2000 [3] LINEAR Technology Company, , “LTC3250-1.2, High Efficiency, Low Noise, Inductorless Step-Down DC-DC Converter”, data sheet, 2001 [4] V. W. Ng, M. D. Seeman, and S. R. Sanders, “Minimum PCB footprint point-of-load DC–DC converter realized with switched-capacitor architecture, ”in Proc. IEEE Energy Convers. Congr. Expo., Feb. 2009, pp. 1575–1581 [5] V. Ng and S. Sanders, “A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converter,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , Feb. 2012, pp. 282–284 [6] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched-capacitor dc-dc converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 841–851, Feb. 2008 [7] M. D. Seeman, V. W. Ng, H.-P Le, M. John, E. Alon, and S. R. Sanders, “A comparative analysis of switched-capacitor and inductor-based DC-DC conversion technologies,” in Proc. IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL), Jun. 2010, pp. 1-7. [8] LINEAR Technology Company, “LTC3251-1.2, 500mA High Efficiency, Low Noise, Inductorless Step-Down DC-DC Converter”, data sheet, 2003 [9] Texas Instruments Company, “LM2772 Low-Ripple Switched Capacitor Step-Down Regulator”, Data Sheet, Dec. 2006 [10] Texas Instruments Company, “LM2770 High Efficiency Switched Capacitor Step-Down DC-DC Regulator with Sleep Mode”, Data Sheet, Dec. 2006 [11] G. A. Rincon-Mora, “Current Efficient, Low Voltage, Low Drop-out Regulators”, Ph.D Thesis, Grorgia Institute of Technology, Nov. 1996 [12] F. Goodenough, “Low Dropout Linear Regulators,” Electronic Design, pp. 65-77, May 13, 1996. [13] G. Di Cataldo, G. Palumbo, “Design of an Nth order Dickson charge pump,” IEEE Trans. CAS I, vol. 43, pp. 414-418, 1996. [14] Phillip E. Allen, Doulas R. Holberg, CMOS Analog Circuit Design. Oxford University, 2002 [15] Walt Kester, Brain Erisman, Gurjit Thandi, “Switched Capacitor Voltage Converters”, Application Note, Analog Device Inc [16] Texas Instruments Company, “Line and Load Regulation for Programmable DC Power Supplies and Precision DC Sources”, Application Note, May, 2014 [17] Texas Instruments Company, “TPS60503 High Efficiency, 250-mA, Step-Down Charge Pump”, data sheet, Oct, 2001 [18] Behzad Razavi, Design of Analog CMOS Integrated Circuit. Boston, MA: McGRAW-HILL, p382, 2001 [19] D. F. Hilbiber, “A new semiconductor voltage standard,” in Proc. Int. Solid-State Circuits Conf., Philadelphia, PA, pp. 32–33, Feb. 1964 [20] Sheng-Hsin Liu, “Design of Efficient White LED Driver”, Master Thesis, National Taiwan University, July 2007 [21] Chua-Chin Wang, Yih-Long Tseng, Tzung-Je Lee, and Ron Hu, “High-PSP Bias Circuitry for NTSC SYNC Separation” IEEE International symposium on Circuit and Systems, VOl. 1, May 2004 [22] G. Jovanovic and M. Stojcev, “A Method for Improvement Stability of a CMOS Voltage Controlled Ring Oscillators”, ICEST 2007, vol. 2, pp. 715-718, 2007 [23] V. Michal, “On the low-power design, stability improvement and frequency estimation of the cmos ring oscillator,” in Radioelektronika, 2012 22nd International Conference. IEEE, 2012, pp. 1-4. [24] Takao M yono, Akira Uemoto, Shuhei Kawai, Takashi Iijima, “High-Efficiency Charge-Pump Circuits which Use a 0.5 Vdd-Step Pumping Method”, IEICE Transactions on Fundationals of Electronics, Vol. E86-A, NO. 2, February 2003 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18353 | - |
dc.description.abstract | 現今行動電子產品使用越來越普及,相關應用技術需求也快速成長。安裝鋰電池為蓄能設備,以及使用通用序列匯流排作為標準充電電源,為現行手持裝置普遍規格。對功率積體電路設計者而言,在電壓供應源之電壓變動下,如何克服產品的功率消耗問題與提高電源轉換效率成為當今重要的研究課題。本論文詳細討論一個應用於手持電子產品之降壓式電壓轉換電路之設計與實現,內容中電路採用多轉換模態電荷汞之電路架構,搭配邏輯控制電路及時脈阻斷回授控制與以實現降壓效果及穩壓能力。本論文設計的電荷汞電路具有五種分數型式之轉換倍率,在電源電壓改變時,電荷汞仍能自動更換降壓倍率以達成轉換效率之最佳化實現;此外,一個時脈訊號放大技術設計被使用以降低開關切換過程中造成的電荷損耗。再者,以時脈訊號阻斷技術的應用取代原有技術在輸出端串聯低壓降線性穩壓電路,在減少能量消耗同時仍能兼顧輸出電壓的穩定性。運用以上所提及之解決方案,本篇提出的電賀汞擁有比較現有技術優良之電壓轉換效率,如此可在有限的電池儲蓄容量下,電子產品工作時間可以被有效延長。
整個高效率電荷汞電路設計是透過台積電2P4M 0.35 5V CMOS製程實現,設計電路設計工作在輸入電壓變動在3.3至5.5V時,輸出電壓保持在1.2伏特,最大負載大小為250mA。所設計之電荷汞量測結果為部分工作,在50mA輸出,輸入電壓為4V時,最高電壓轉換效率為56%,最低轉換效率為49.6%。 | zh_TW |
dc.description.abstract | Today, portable electrical devices are more and more popular, and so the relating applying technologies are also fast-growing. The general standard specifications for mobile devices has become Li-ion batteries as the energy storage unit and charging by USB. For the IC designer, overcoming the power dissipation problem and raising the power efficiency has become an important research topic. This thesis presents a buck mode converter designed for portable devices. The charge pump is assembled with a multiple voltage conversion gains switch array, a control circuit and a feedback network, and the designed circuit is employed to transfer voltage down and provides a regulated voltage for load. Since the presented charge pump contains five types of fractional conversion gains to transfer voltage, when the power source changes its voltage level, the charge pump can switch to different conversion gains automatically to optimize the power efficiency. Moreover, a clock boosting technique is utilized to alleviate the charge loss during the duration of switches turning on. Furthermore, the clock block technique can maintain a regular voltage and reduce loss at the same time. Combined with the aforementioned solutions, the charge pump reported in this thesis contains superior power efficiency when compared to a conventional product. With the charge pump, as compared to conventional products under same battery capacity conditions, the operation time of electrical devices will be extended efficiently. The overall circuits included in the charge pump are simulated and processed by TSMC 2P4M 0.35μm 5V CMOS process, with a functional range between 5.5 to 3.3V, and a loading current of up to 250mA at 1.2 volts. The measurement result shows that the designed circuit is partial work. In the first version, the maximum power efficiency is 56% and the minimum power efficiency is 49.6% under the 50mA loading and 4V input voltage. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:01:05Z (GMT). No. of bitstreams: 1 ntu-103-R01942078-1.pdf: 3767292 bytes, checksum: 3985e8de21663cadf283492a6d2b515f (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 誌謝 I
中文摘要 II ABSTRACT III CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XIII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 PAPER SURVEY 6 1.3 MOTIVATION 11 1.4 RESEARCH GOALS AND CONTRIBUTIONS 12 1.5 THESIS ORGANIZATION 12 CHAPTER 2 FUNDAMENTALS OF STEP-DOWN DC-DC CONVERTERS 14 2.1 TYPES OF STEP-DOWN DC-DC CONVERTER 14 2.1.1 Low Dropout Regulator 14 2.1.2 Charge Pumps 18 2.1.3 Switching Regulators 22 2.2 SPECIFICATIONS OF CHARGE-PUMPS 28 2.2.1 Ground Current and Quiescent Current 28 2.2.2 Efficiency 29 2.2.3 Load Regulation 31 2.2.4 Line Regulation 32 2.2.5 Power Supply Rejection Ratio 33 2.3 VOLTAGE CONVERSION GAIN AND SWITCHED-ARRAY ARCHITECTURE 34 2.3.1 Voltage Conversion Gain 35 2.3.2 Fraction Gain Switched-Array Architecture 38 2.4 POWER DISSIPATION 41 2.4.1 Conduction Loss 42 2.4.2 Dynamic Power Loss 45 CHAPTER 3 EFFICIENT CHARGE-PUMP DESIGN 47 3.1 ARCHITECTURE 47 3.2 BAND-GAP REFERENCE 49 3.3 COMPARATOR CIRCUIT 57 3.4 OSCILLATOR CIRCUIT 60 3.5 CONTROL CIRCUIT 62 3.6 NON-OVERLAPPING CLOCK GENERATOR 66 3.7 GATE DRIVER CIRCUIT 67 3.8 SWITCH-CAPACITOR ARRAY 71 3.9 CLOCK BLOCK CONTROL CIRCUIT 77 3.10 SIMULATION 78 CHAPTER 4 IMPROVED DESIGN OF CHARGE-PUMP 82 4.1 MOTIVATION 82 4.2 IMPROVED RIPPLE 83 4.3 IMPROVED SPUR 85 4.4 IMPROVED RELIABILITY 89 4.5 SIMULATION 91 CHAPTER 5 MEASUREMENT 95 5.1 MEASUREMENT ENVIRONMENT AND SETUP 96 5.2 THE FIRST VERSION MEASUREMENT RESULTS 97 5.3 THE SECOND VERSION MEASUREMENT RESULT 101 5.4 MEASUREMENT RESULT ANALYSIS 103 CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 107 6.1 CONCLUSIONS 107 6.2 FUTURE WORK 108 REFERENCES 109 | |
dc.language.iso | en | |
dc.title | 適用於大電流輸出之降壓式電荷汞 | zh_TW |
dc.title | A Buck Mode Charge Pump Operating under Large Current Output | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳信樹(Hsin-Shu Chen),劉邦榮(Pang-Jung Liu) | |
dc.subject.keyword | 電荷汞,轉換器, | zh_TW |
dc.subject.keyword | charge pump,converter, | en |
dc.relation.page | 111 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2014-12-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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ntu-103-1.pdf 目前未授權公開取用 | 3.68 MB | Adobe PDF |
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