一個0.4伏特單次存取能量消耗4.76微微焦耳11.6百萬赫芝1千位元靜態隨機存取記憶體具有提出的單端存取7個電晶體記憶單元並使用寫入與讀取偵測技術

Abstract

在本篇論文中，一個0.4伏特單次存取能量消耗4.76微微焦耳11.6百萬赫芝1千位元靜態隨機存取記憶體被實現，以台積電90奈米互補式金氧半製程製造完成。由於單端存取的機制，與傳統的6個電晶體記憶單元相比，所提出的7個電晶體記憶單元消耗較少功率。回授路徑切斷與讀取分離式技術，可使所提出的7個電晶體記憶單元擁有更好的寫入邊限與讀取雜訊邊限。為了達成製程、電壓以及溫度的變異容忍，在不損害總功率的情況下，以複製單一列記憶單元與複製單一行記憶單元來實現寫入與讀取偵測技術。測試晶片的量測結果顯示從1.0伏特到0.4伏特皆呈現低能量消耗，並且與後模擬結果相符。最後，採用這些技術後，實現了穩定且低能量消耗的靜態隨機存取記憶體，可以被使用在對能量有限制的應用中。

In this thesis, a 400mV 4.76pJ/Access 11.6MHz 1Kb SRAM is implemented in TSMC 90nm 1P9M CMOS process. Due to single-ended access, the proposed 7T SRAM cell consumes less power compared to the traditional 6T SRAM cell. With the feedback-loop-cutting scheme and the read-separated scheme, the proposed 7T SRAM cell possesses better write margin (WM) and read static noise margin (RSNM). To achieve PVT variation tolerance, the write and read detecting scheme is implemented by the single row repeat (SRR) circuit and the single column repeat (SCR) circuit without compromising the total power consumption. Measurement results of a test chip show that the proposed SRAM system consumes low energy from 1.0V to 0.4V, and agree with the post-simulation results. Finally, these schemes achieve the stable and low-energy consumption SRAM, which can be used in energy-constraint applications.