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標題: | 應用於小面積與背景校正供應電壓雜訊之鎖相迴路 Applications of Phase-Locked Loops with Area-Efficiency and Background Supply Noise Cancellation |
作者: | Che-Wei Yeh 葉哲維 |
指導教授: | 劉深淵(Shen-Iuan Liu) |
關鍵字: | 鎖相迴路,次諧波注入鎖定,相位雜訊,無除頻器,供應電壓雜訊,方均根抖動, phase-locked loop,sub-harmonically injection-locked,phase noise,divider-less,supply-noise,jitter, |
出版年 : | 2015 |
學位: | 碩士 |
摘要: | 這篇論文的主題主要分為兩個部分,第一部分實現了一個具有小面積與無除頻器之次諧波注入鎖相迴路。次諧波注入鎖定的技巧被用來壓抑振盪器之相位雜訊。藉由降低迴路濾波器的電容值並同時確保次諧波注入鎖相迴路的穩定性,我們提出了一個小面積的次諧波注入鎖相迴路。除此之外,我們也提出了一個注入時間點校正之技巧去對齊振盪器之最佳注入點。量測到的相位雜訊驗證了次諧波注入鎖相迴路在無除頻器時,有較佳的雜訊效能,相較於有除頻器的情況。方均根抖動量為0.64ps,總面積為0.0074mm2.
第二部分實現了一個背景校正供應電壓雜訊的全數位鎖相迴路。我們使用了供應雜訊電流消去的做法來改善因為振盪器的供應電壓有雜訊存在所造成方均根抖動量變差的情況。我們提出了一個數位校正的方式去精準校正全數位鎖相迴路在不同製程、電壓、溫度引起的變異。在振盪器的供應電壓注入峰對峰值為50 mV,頻率為10 kHz的弦波雜訊時,量測到的峰對峰值抖動量從原本的41.87 ps降低至29.11 ps。量測到的方均根抖動量從原本的 4.43 ps 降低到 4.03 ps。經由供應電壓雜訊所引起的突波從原本的 -13.88 dB降低到 -25.41 dB。在未注入供應電壓雜訊時,量測到的峰對峰值和方均根抖動量分別為 29 ps 和 3.4ps。此全數位鎖相迴路的功耗和面積分別為2.915 mW 以及0.0216mm2. This thesis consists of two parts. The first part implements an area-efficient divider-less sub-harmonically injection-locked PLL (SIPLL). Sub-harmonically injection-locked technique is employed to suppress VCO accumulation noise. Besides, an area-efficient SIPLL is present to reduce the capacitor in the loop filter, which also ensures the SIPLL to be stable. In addition, a self-adjusted injection timing method is also proposed. The measure phase noise validates the better performance without a divider compared with that with a divider. The RMS jitter is 0.64 ps. Moreover, the total area is 0.0074 mm2. The second part implements a digital phase-locked loop (DPLL) with background supply noise cancellation. The DPLL employs supply noise current cancellation to mitigate jitter performance degradation due to supply noise on the oscillator supply voltage. A digital background cancellation is proposed to accurately cancel the supply noise under different process, and temperature conditions. In the presence of a 50 mVPP 10 kHz sinusoidal supply noise tone, the cancellation scheme reduces the peak-to-peak jitter from 41.87 ps to 29.11 ps. The rms jitter is reduced from 4.43 ps to 4.03 ps and the spurious supply noise spur is improved from -13.88 dB to -25.41 dB. In the absence of any supply noise, the peak-to-peak jitter and rms jitter are 29 ps and 3.4ps, respectively. The power consumption is 2.915mW and its active area is 0.0216mm2. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18069 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-104-1.pdf 目前未授權公開取用 | 4.71 MB | Adobe PDF |
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