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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | |
dc.contributor.author | Ching-Kai Kao | en |
dc.contributor.author | 高靖凱 | zh_TW |
dc.date.accessioned | 2021-06-08T00:48:36Z | - |
dc.date.copyright | 2015-07-21 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-17 | |
dc.identifier.citation | [1] T. Hamamoto, S. Sugiura, and S. Sawada, “On the Retention Time Distribution of
Dynamic Random Access Memory (DRAM),” IEEE Trans. Electron Devices, vol. 45 no. 6, pp. 1300-1309, June 1998. [2] K. Saino et al., “Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time,” in IEDM Tech. Dig. 2000, pp. 837–840. [3] H. Kim, B. Oh, Y. Son, K. Kim, S.Y. Cha, J. G. Jeong, S. J. Hong, and H. Shin, ” Characterization of the Variable Retention Time in Dynamic Random Access Memory,” IEEE Tran. Electron Devices, vol. 59, no. 9, pp.2952-2958, September 2002. [4] A.Weber, A. Birner, andW. Krautschneider, “Method of activation energy analysis and application to individual cells of 256 Mb DRAM in 110 nm technology,” Solid State Electron., vol. 50, no. 4, pp. 613–619, Apr. 2006. [5] International Technology Roadmap for Semiconductors (ITRS): 2007. [6] T. Osabe, et al, 'A Single-Electron Shut-Off Transistor for a Scalable Sub-0.1 um Memory', (Hitachi) IEDM, December 2000, pp301. [7] K. Nakazato, et al, 'Phase-state Low Electron-number Drive Random Access Memory (PLEDM)', ISSCC, February 2000, pp132. [8] J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, “RTD/HFET Low Standby Power SRAM Gain Cell,” IEEE Electron Device Letters, vol. 19, no. 1, Jan. 1998. [9] P. van der Wagt, A.C. Seabaugh, and E. Beam, 'RTD/HFET Low Standby Power SRAM Gain Cell', (Texas Instruments), IEDM, December 1996, pp425. [10] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, pp.230, 1957. [11] C. C. Ting, Y. H. Shih, and J. G. Hwu, “Ultralow Leakage Characteristics of Ultrathin Gate Oxides (~3 nm) Prepared by Anodization Followed by High-Temperature Annealing,” IEEE Tran. Electron Devices, vol. 49, no. 1, pp.179-181, 2002. [12] M. J. Jeng, “Application of Anodic Oxidation and Rapid Thermal Treatment on Thin Gate Oxides and Radiation-Hardness CMOS sensing circuit,” Ph.D. dissertation, Dept. Elect. Eng., Nat Taiwan Univ., Taipei, Taiwan, R.O.C., 1996. [13] S. K. Ghandhi, VLSI Frabrication Principles, 2nd ed., Wiley-Interscience, pp. 487-495, 1994. [14] K. Yang, C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46 no. 7, pp. 1500-1501, July 1999. [15] E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York: Wiley, pp. 74,1981. [16] Y.-K. Lin, L. Lin, and J.-G. Hwu, “Minority carriers induced Schottky barrier height modulation in current behavior of metal–oxide–semiconductor tunneling diode,” ECS J. Solid State Sci. Technol., vol. 3, no. 6, pp. Q132–Q135, May 2014. [17] Y.P. Lin and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” J.Electrochem. Soc., vol 151, no. 12, pp. G853-G857, Oct. 2004. [18] S. Altindal, I. Dokme, M. M. Bulbul, N. Yalcin, and T. Serin, ” The Role of the Interface Insulator Layer and Interface States in the Current-transport Mechanism of Schottky Diodes in Wide Temperature Range,” Microelectron. Eng., vol. 83, no. 3, pp. 499-505, Mar. 2006. [19] I. Dokme, S. Altindal, “On the Intersecting Behavior of Experimental Forward Bias Current-voltage (I-V) Characteristics of Al/SiO2/p-Si (MIS) Schottky Diodes at Low Temperatures,” Semicond. Sci. Technol., vol. 21, no. 8, pp. 1053-1058, June. 2006. [20] S. W. Huang and J. G. Hwu, “Electrical Characterization and Process Control of Cost-Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing,” IEEE Trans. Electron Devices, vol. 50, no. 7, Jul. 2003. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18016 | - |
dc.description.abstract | 在本篇論文中, 我們製作了一個介電堆疊層為 氧化鋁/鋁/二氧化矽 的金氧半電容元件並在此元件中發現了兩態特性。在第二章,我們說明了此兩態特性是源自於暫態電流。而暫態電流的來源是因為在寫入元件時,電荷儲存在内嵌鋁而導致。為了能清楚分辨正負電流,我們會在'最佳讀取電壓'去讀取元件。如此一來,將可以得到一組'對稱'的正負電流對。另外,我們發現當寫入電壓提高時,兩態櫥窗也會跟著變大。最後,我們得到元件的資料保存時間大約是1.1秒。在第三章,我們找到了三個可以影響兩態櫥窗的因素。第一,我們觀察到當二氧化矽的厚度越薄時,元件會呈現更大的兩態櫥窗。第二,當元件經過了後金屬退火處理之後,兩態效應會變得更明顯,而這是因為後金屬退火處理會使二氧化矽的厚度局部變薄。第三,內嵌鋁的氧化時間也是一個很重要的因素。當內嵌鋁的氧化時間很長時,二氧化矽厚度會變厚而且中間的內嵌鋁會全部被氧化。基於上述兩個原因,兩態櫥窗幾乎消失不見。 | zh_TW |
dc.description.abstract | In this thesis, a MOS capacitor with Al2O3/Al/SiO2 dielectric stack structure was fabricated and it is observed that there is a two-state characteristic in this device. In chapter 2, it is shown that the two-state characteristic results from the two-state transient currents and the two-state transient currents are caused by the charges stored in the embedded aluminum. In order to distinguish the two states clearly, it is suggested to read the device at the 'best read voltage'. This 'best read voltage' would lead to a 'symmetrical' two-state current pair. It is also noticeable that the two-state window would be larger if the writing voltages are larger and the retention time of our device is about 1.1s. In chapter 3, three factors that could influence the two-state window are discussed. First, it is observed that the two-state window would be larger if the thickness of SiO2 is smaller. Second, it is found out that after post metallization annealing, the two-state window would be larger, which results from the local thickness reduction of SiO2 after PMA. Third, the oxidation time of embedded aluminum is also an important factor. If the oxidation time of embedded aluminum is very long, the thickness of SiO2 would be larger and the embedded aluminum would be totally oxidized. Owing to the thick SiO2 and the absence of embedded aluminum, the two-state window almost disappears. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:48:36Z (GMT). No. of bitstreams: 1 ntu-104-R02943071-1.pdf: 4864088 bytes, checksum: 418136c108aaf88d0a6dab3233d5b56f (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | Abstract(Chinese)………………………………………………………………….I
Abstract(English)………………………………………………………………….II Contents……………………………………………………………………………..III Figure Captions…………………………………………………………………..VI Chapter 1 Introduction 1-1 Retention Time of Dynamic Random Access Memory……………………..2 1-2 About This Work…………………………………………………………….5 1-3 Anodic Oxidation System……………………………………………………7 1-4 Summary……………………………………………………………………..8 Chapter 2 Two-State Characteristics of Al2O3 / Al / SiO2 Dielectric Stack Structure 2-1 Introduction…………………………………………………………………14 2-2 Experimental Procedure…………………………………………………….14 2-3 Results and Discussion……………………………………………………15 2-3-1 C-V Characteristics…………………………………………………15 2-3-2 Two-State Characteristic and Its Mechanism of Al2O3/Al/SiO2 Stack Structure…………………………………………………………………16 2-3-3 Different Writing Voltages…………………………………………..17 2-3-4 The Best Read Voltages for Various Writing Voltages………………18 2-3-5 Endurance and Retention Characteristics…………………………..19 2-4 Summary……………………………………………………………………20 Chapter 3 Influencing Factors of the Two-State Windows 3-1 Introduction…………………………………………………………………31 3-2 Experimental Procedure…………………………………………………….31 3-2-1 Various Thicknesses of SiO2 ..............................................................31 3-2-2 With and Without Post Metallization Annealing (PMA)……………32 3-2-3 Anodic Oxidation Time of Embedded Aluminum…………………33 3-3 Results and Discussion……………………………………………………33 3-3-1 Comparison among Various Thicknesses of SiO2…………………33 3-3-1-1 The C-V and J-V of the Control Sample……………………33 3-3-1-2 Two-state Window Comparison among Various Thicknesses of SiO2…………………………………………………………………34 3-3-2 Comparison between PMA (with PMA) and NOPMA (without PMA)………………………………………………………………………34 3-3-3 Anodic Oxidation Time of Embedded Aluminum………………...37 3-4 Summary……………………………………………………………………38 Chapter 4 Conclusions and Suggestions for Future Work 4-1 Conclusions…………………………………………………………………52 4-2 Suggestions for Future Work………………………………………………54 References………………………………………………………………………….56 | |
dc.language.iso | en | |
dc.title | 氧化鋁/鋁/二氧化矽介電堆疊金氧半電容元件中兩態電流現象 | zh_TW |
dc.title | Two-State Current Phenomenon in MOS Device with
Al2O3/Al/SiO2 Dielectric Stack Structure | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林浩雄,鄭晃忠 | |
dc.subject.keyword | 揮發性記憶體,兩態現象,保存時間,金氧半元件,內嵌鋁, | zh_TW |
dc.subject.keyword | volatile memory,two states,retention time,MOS device,embedded Al, | en |
dc.relation.page | 59 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-07-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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