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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Wei-Hsiang Huang | en |
dc.contributor.author | 黃偉翔 | zh_TW |
dc.date.accessioned | 2021-06-08T00:48:02Z | - |
dc.date.copyright | 2015-07-23 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-22 | |
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Fiez ”A 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 487-501, Feb. 2013. [20] K. Matsukawa, K. Obata,Y. Mitani ,and S. Dosho, “A 10 MHz BW 50 fJ/conv. Continuous Time ΔΣ Modulator with High-Order Single Opamp Integrator Using Optimization-Based Design Method,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2012, pp. 160-161. [21] C.-H. Weng, T.-A Wei, E. Alpman*, C.-T. Fu*, Y.-T. Tseng, and T.-H. Lin, “An 8.5MHz 67.2dB SNDR CTDSM with ELD Compensation Embedded Twin-T SAB and Circular TDC-based Quantizer in 90nm CMOS” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2014, pp. 106-107. [22] C.-L. Lo, C.-Y. Ho, H.-C. Tsai, and Y.-H. Lin, “A 75.1dB SNDR 840MS/s CT ΔΣ Modulator with 30MHz Bandwidth and 46.4fJ/conv FOM in 55nm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2013, pp. 60-61. [23] M. Park and M. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17995 | - |
dc.description.abstract | 本論文包含兩個作品。第一個作品是一個四階四位元連續時間型三角積分調變器,迴路濾波器的部分使用兩個單運算放大器濾波器來實現,因此四階誤差整形只需要兩個運算放大器及兩個數位類比轉換器。量化器的部分採用低延遲的快閃式架構,所提出的隨機跳躍資料加權平均可以解決量化器及回授數位類比轉換器中元件不匹配所產生的非線性問題。此三角積分調變器使用台積電90奈米互補式金氧半製程所實現,在使用320 MHz的取樣頻率在13 MHz的頻寬下可以得到68 dB的訊號雜訊比和72.3 dB的動態範圍,在1.2伏特的供應電源、回授數位類比轉換器採用1.6伏特時,只需要消耗5.1毫瓦的功率,且FoM為95 fJ/conv-step。
第二個作品是一個四階三位元連續時間型三角積分調變器,迴路濾波器的部分使用一個積分器與單運算放大器濾波器來實現。量化器的部分採用內建資料加權平均的壓控震盪器,由於迴路濾波器的高增益加上使用兩個單端的壓控震盪器來達到偽差動的效果,壓控震盪器的非線性便可以被消除。此外,兩組數位類比轉換器間的差異可以被隨機交換機制所消除。此三角積分調變器使用台積電90奈米互補式金氧半製程所實現,在使用MHz的取樣頻率在8 MHz的頻寬下可以得到67.5 dB的訊號雜訊比和73.1 dB的動態範圍,在1.2伏特的供應電源、回授數位類比轉換採用1.6伏特時,只需要消耗4.4毫瓦的功率,且FoM為142 fJ/conv-step。 | zh_TW |
dc.description.abstract | Two works are included in this thesis. The first work is a 4th-order 4-bit CTDSM. With proposed SAB-based loop filter, 4th-order noise shaping is achieved with two local resonators while using only two op-amps and two DACs. A low-power interpolating flash quantizer with an embedded random-skipped incremental data weighted averaging (RS-IDWA) function is presented. The proposed RS-IDWA function addresses nonlinearity issues of the quantizer and feedback DACs. Fabricated in 90 nm CMOS, the proposed CTDSM achieves peak SNDR of 68 dB over 13 MHz signal bandwidth, while consuming 5.1 mW at 320 MHz sampling frequency, and scores an FoM of 95 fJ/conv.-step.
The second work is a 4th-order 3 bit CTDSM consisting of SAB-based loop filter and VCO-based-quantizer. With the high gain of preceding 3rd-order loop filter and using two VCO-based quantizer in a pseudo-differential manner, nonlinearity in the transfer curve can be suppressed. Mismatch in two DAC segments are further linearized with proposed PRBS function. Fabricated in 90 nm CMOS, the proposed CTDSM achieves peak SNDR of 67.5 dB over 8 MHz signal bandwidth, while consuming 4.4 mW at 360 MHz sampling frequency, and scores an FoM of 142 fJ/conv.-step. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:48:02Z (GMT). No. of bitstreams: 1 ntu-104-R02943001-1.pdf: 5022315 bytes, checksum: e2b55d14cbbb009dd4035784f5a53aec (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | CHAPTER 1. INTRODUCTION 1
1.1 RESEARCH MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2. BACKGROUND ON DELTA-SIGMA MODULATORS 5 2.1 ISSUES OF CTDSM 5 2.2 ANTI-ALIASING BEHAVIOR 5 2.3 FEEDBACK REALIZATION 8 2.4 EXCESS LOOP DELAY 11 2.5 DYNAMIC ELEMENT MATCHING (DEM) 16 CHAPTER 3. DESIGN AND IMPLEMENTATION OF THE CTDSM WITH SAB-BASED LOOP FILTER AND RS-IDWA EMBEDDED INTERPOLATING FLASH QUANTIZER 23 3.1 MOTIVATION 23 3.2 DESIGN CONSIDERATIONS OF SINGLE-AMPLIFIER-BIQUAD (SAB) TOPOLOGY AND SAB-BASED CTDSM 24 3.2.1 INTRODUCTION OF SAB TOPOLOGY 24 3.2.2 PRIOR ARTS OF SAB TOPOLOGY 26 3.2.3 MODIFIED TWIN-T SAB WITH FEEDFORWARD PATH 28 3.2.4 PROPOSED SAB-BASED LOOP FILTER TOPOLOGY 30 3.3 INTERPOLATING FLASH QUANTIZER WITH AN EMBEDDED RANDOM-SKIPPED INCREMENTAL DATA WEIGHTED AVERAGING (RS-IDWA) FUNCTION 32 3.3.1 INTERPOLATING FLASH QUANTIZER 32 3.3.2 REFERENCE SHUFFLING TECHNIQUE 34 3.3.3 PROPOSED RS-IDWA 37 3.4 SYSTEM DESIGN AND CIRCUIT IMPLEMENTATION 44 3.4.1 SYNTHESIZING OF LOOP FILTER 45 3.4.2 DESIGN OF OPERATIONAL AMPLIFIER (OP-AMP) 47 3.4.3 DESIGN OF COMPARATOR 48 3.4.4 DESIGN OF FEEDBACK DAC 49 3.5 SIMULATION RESULTS 51 3.6 EXPERIMENTAL RESULTS 55 3.6.1 MEASUREMENT ENVIRONMENT 56 3.6.2 MEASUREMENT RESULTS 57 CHAPTER 4. DESIGN AND IMPLEMENTATION OF THE CTDSM WITH SAB-BASED LOOP FILTER AND VCO-BASED QUANTIZER 61 4.1 MOTIVATION 61 4.2 DESIGN CONSIDERATIONS OF VCO-BASED ADCS 62 4.2.1 PRIOR ARTS OF VCO-BASED ADCS 62 4.2.2 LINEARITY IMPROVEMENT USING TWO SINGLE-ENDED VCO-BASED QUANTIZERS IN A PSEUDO-DIFFERENTIAL MANNER 63 4.2.3 USING PRBS FUNCTION TO IMPROVE THE MISMATCH BETWEEN TWO INDEPENDENT DWA FUNCTION 65 4.2.4 ELD COMPENSATION FOR A CTDSM WITH A VCO-BASED QUANTIZER 67 4.3 TOPOLOGY OF PROPOSED CTDSM WITH VCO-BASED QUANTIZER 70 4.4 SYSTEM DESIGN AND CIRCUIT IMPLEMENTATION 72 4.4.1 SYNTHESIZING OF LOOP FILTER 72 4.4.2 DESIGN OF VCO-BASED QUANTIZER 74 4.4.3 SYSTEM VERIFICATION 75 4.5 SIMULATION RESULTS 77 4.6 MEASUREMENT RESULTS 81 CHAPTER 5. CONCLUSION 89 | |
dc.language.iso | en | |
dc.title | 使用SAB濾波器與內建資料加權平均之量化器之連續時間三角積分調變器 | zh_TW |
dc.title | Design of a Continuous-Time Delta-Sigma Modulator with Single-Amplifier-Biquad (SAB) Filter and DWA-Embedded Quantizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭泰豪(Tai-Haur Kuo),許雲翔(Yun-Shiang Shu),謝志成(Chih-Cheng Hsieh),蔡宗亨(Tsung-Heng Tsai) | |
dc.subject.keyword | 連續時間三角積分調變器, | zh_TW |
dc.subject.keyword | Continuous-Time Delta-Sigma Modulator, | en |
dc.relation.page | 95 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-07-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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