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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 莊東漢 | |
dc.contributor.author | Chun-Hao Chen | en |
dc.contributor.author | 陳俊豪 | zh_TW |
dc.date.accessioned | 2021-06-08T00:47:12Z | - |
dc.date.copyright | 2015-08-04 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-27 | |
dc.identifier.citation | [1] C. A. Giffels, R J. Gashler, J. M. Morabito and K. M. Striny, “Interconnection Media”, AT&T Technical Journal, Vol. 66, No. 4 (1987) pp. 31-44.
[2] M. R. Pinnel and W. H. Knausenberger, “Interconnection System Requirements and Modeling”, AT&T Technical Journal, Vol. 66, No. 4 (1987) pp. 45-56. [3] J. H. Lau, “Ball Grid Array Technology”, McGraw-Hill, New York (1995) pp.2. [4] Moore, Gordon E. (1965). 'Cramming more components onto integrated circuits'. Electronics Magazine. p. 4. [5] Brock, David C., ed. (2006). Understanding Moore's law: four decades of innovation. Philadelphia, Pa: Chemical Heritage Press. ISBN 0941901416. [6]'1965 – 'Moore's Law' Predicts the Future of Integrated Circuits'. Computer History Museum. 2007. [7] User Wgsimon. (May 13, 2011). Microprocessor Transistor Counts 1971-2011 & Moore’s Law. Abstract retrieved from March 30, 2015, from http://en.wikipedia.org/wiki/Moore%27s_law#/media/File:Transistor_Count_and_Moore%27s_Law_-_2011.svg [8] Directive 2011/65/EUof the European Parliament and of the Council of 8 June 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. [9] J. Y. Chang, R. S. Cheng, K. S. Kao, T.C. Chang, and T. H. Chuang,” Reliable Microjoints Formed by Solid –Liquid Interdiffusion (SLID) Bonding Within a Chip-Stacking Architecture”, IEEE Trans. Comp. Pack. Manuf. Technol., vol.2, 2012, pp.979-984. [10] Y.K. Lee, Y. H. Ko, J. K. Kim, C. W. Lee, S. Yoo, The effect of intermetallic compound revolution on the fracture behavior of Au stud bumps joined with Sn-3.5Ag solder, Electron. Mater. Lett., 9 (2013) 31-39. [11] M. S. Shin, Y. H. Kim, Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads, Journal of Elec Materi, 32 (2003) 1448-1454. [12] M. H. Jeong, Y. B. Park, Interfacial reaction kinectics in Au stud/Sn bumps during annealing and current stressing, Current Applied Physics, 11 (2011) S124-S127. [13] 蕭宏(2013)。半導體製程技術導論(修訂二版) (陳啟文、許重傑、蔡有仁、溫榮弘、楊銀堂、段寶興 譯)。 新北市 全華圖書股份有限公司。 [14] George Riley (Nov., 2011). Solder Bump Flip Chip. Abstract retrieved from March 31, 2015, from http://flipchips.com/tutorial/bump-technology/solder-bump-flip-chip/ [15] 莊東漢等 (2014)。銀合金銲球凸塊覆晶組裝及其應用。電子月刊第二十卷 第十期。 [16] 'R107 Flip Chip Top' by Douglas W. Jones - Own work. Licensed under CC0 via Wikimedia Common http://commons.wikimedia.org/wiki/File:R107FlipChipTop.JPG#/media/File:R107FlipChipTop.JPG [17] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi and A. Nitayama, 'Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory ', Symposium on VLSI Technology Digest of Tech Papers, pp. 14-15, 2007. [18] Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi and A. Nitayama, 'Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory', IEDM Technical Digest, pp. 449-452, 2007. [19] J.H. Lau, Ball Grid Array Technology, McGraw-Hill, 1995. [20] G.R. Blackwell, The Electronic Packaging Handbook, Taylor & Francis, 1999. [21] Myong-Hoon Roh, Jae Pil Jung, Wonjoong Kim, “Microstructure, shear strength, and nanoindentation property of electroplated Sn–Bi micro-bumps”, Microelectronics Reliability 54 (2014) 265–271. [22] R. Kiumi, S. Takeda, J. Yoshioka, F. Kuriyama, N. Saito, Composition control for lead-free alloy electroplating on flip-chip bumping, Electronic Components and Technology Conference, 2005. Proceedings. 55th, 2005, pp. 120-126 Vol. 121. [23] “全自動錫膏印刷鋼板的最佳化製程2”。Abstract retrieved from May 1, 2015, from http://dsp168smt.blog.china.com/201208/10057390.html [24] Anita Brown, “Indium Corporation Announces Void-Reducing Water-Soluble Solder Paste”, Indium Corporation, 2 May 2013. [25] C.L. Wong, James How, “Low Cost Flip Chip Bumping Technologies”, IEEWCPMT Electronic Packaging Technology Conference, 1997. pp 244-250. [26] C. Ghosh, Interdiffusion study in binary gold-tin system, Intermetallics, 18(2010) 2178-2182. [27] P.G. Kim, K.N. Tu, Fast dissolution and soldering reactions on Au foils, Materials Chemistry and Physics, 53(1998) 165-171. [28] Y. Myung-Jin, H. Jin-Sang, K. Woonseong, J. Kyung Woon, P. Kyung-Wook, Highly reliable non-conductive adhesives for flip chip CSP applications, Electronics Packaging Manufacturing, IEEE Transactions on, 26 (2003) 150-155. [29] L. Daoqiang, C.P. Wong, A study of contact resistance of conductive adhesives based on anhydride-cured epoxy systems, Components and Packaging Technologies, IEEE Transactions on, 23 (2000) 440-446. [30] L. Daoqiang, C.P. Wong, Development of solder replacement conductive adhesives with stable resistance and superior impact performance, Adhesive Joining and Coating Technology in Electronics Manufacturing, 2000, Proceedings, 4th International. [31] C. K. Lee, T. C. Chang, Y. J. Huang, H. C. Fu, J. H. Huang, Z. C. Hsiao, J. H. Lau, C. T. Ko, R. S. Cheng, P. C. Chang, K. S. Kao, Y. L. Lu, R. Lo, and M. J. Kao, “Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration,” in Proc. Electron. Compon. Technol. Conf., Lake Buena Vista, FL, 2011, pp. 1468–1474. [32] J.-Y. Chang, R.-S. Cheng, K.-S. Kao, T-C. Chang, T.-H. Chuang, “Reliable Microjoints Formed by Solid-Liquid Interdiffusion (SLID) Bonding Within a Chip-Stacking Architechture.” IEEE Transactions on components, Packaging and Manufacturing Technology, Vol. 2, No. 6, June (2012) pp. 979-984. [33] X. Guowei, P. Chan, J. Cai, A. Teng, M. Yuen, The effect of Cu stud structure and eutectic solder electroplating on intermetallic growth and reliability of flip-chip solder bump, Electronic Components & amp; Technology Conference, 2000. 2000 proceedings. 50th, 2000, pp. 54-59. [34] G. Humpston, D.M. Jacobson, S.P.S. Sangha, Diffusion soldering for electronics manufacturing, Endeavour, 18 (1994) pp. 55-60. [35] V. Simić, Ž. Marinković, Room temperature interactions in Ag-metals thin film couples, Thin Solid Films, 61 (1979) pp.149-160. [36] J.F. Li, P.A. Agyakwa, C.M. Johnson, Kinetics of Ag3Sn growth in Ag-Sn-Ag system during transient liquid phase soldering process, Acta Materialia, 58 (2010) pp. 3429-3443. [37] T.L. Su, L.C. Tsao, S.Y. Chang, T.H. Chuang, Morphology and growth kinetics of Ag3Sn during soldering reaction between liquid Sn and an Ag substrate, J. of Materi Eng and Perform, 11 (2002) 365-368. [38] B.F. Dyson: J. Appl. Phys., 1996, 37, p. 2375, cited: Diffusion in Solid Metals and Alloys, H. Mehrer, ed., Landorf Bornstein Handbook, Springer Verlag, 1990, 26, p. 157. [39] V.K. Kaygorodov, S.M. Klotsman, A.N. Jimofeyev, and I.Sh. Trakhtenberg: Phys. Met. Metallog., 1969, 28, pp. 128, 146. [40] T. Takenaka, M. Kajihara, K. Sakamoto, Reactive diffusion between Ag-Au alloys and Sn at solid-state temperatures, Materials Transactions, Vol. 46, No. 8 (2005) pp. 1825-1832. [41] T. Sakama, M. Kajihara, Influence of Ag on Kinetics of Solid-State Reactive Diffusion between Pd and Sn, MATERIALS TRANSACTIONS, 50(2009) pp. 266-274. [42] T. Sakama, M. Kajihara, Kinetics of reactive diusion between Pd-Ag alloys and Sn at solid-state temperatures, Journal of Alloys and Compounds, 475 (2009) 608-613. [43] M. Kajihara, Analysis of kinetics of reactive diffusion in a hypothetical binary system, Acta Mater. 52 (2004) 1193-1200. [44] M. Kajihara, Relationship between temperature dependence of interdiffusion and kinetics of reactive diffusion in a hypothetical binary system, Mater. Sci. Eng. A 403 (2005) 234-240. [45] M. Kajihara, Temperature dependence of kinetics for reactive diffusion in a hypothetical binary system, Mater. Trans. 46 (2005) 2142-2149. [46] M. Yamakami, M. Kajihara, Solid-State Reaction Diffusion between Sn and Electrode Ni-P at 473K, Def. Diff. Forum 249 (2006) 91-96. [47] M. Kajihara, Quantitative Evaluation of Interdiffusion in Fe2Al5 during Reactive Diffusion in the Binary Fe–Al System, Mater. Trans. 47 (2006) 1480-1484. [48] Y. Tanaka and M. Kajihara, Evaluation of Interdiffusion in Liquid Phase during Reactive Diffusion between Cu and Al, Mater. Trans. 47 (2006) 2480-2488. [49] M. Kajihara and T. Yamashina, Quantitative analysis for kinetics of reactive diffusion in the Fe–Cr system, J. Mater. Sci. 42 (2007) 2432-2442. [50] M. Kajihara, Influence of Temperature Dependence of Solubility on Kinetics for Reactive Diffusion in a Hypothetical Binary System, Mater. Trans. 49 (2008) 715-722. [51] G. Shamar, C.M. Eichfeld, S.E. Mohney, Intermetallic growth between lead-free solders and Palladium, Journal of Elec Materi, 32 (2003) 1209-1213. [52] R. Ravi, A. Paul, Diffusion and growth mechanism of phases in the Pd-Sn system, J Mater Sci: Mater Electron, 23 (2012) 2306-2310. [53] M. Dusek, I. Szendiuch, J. Bulva, M. Zelinka, Wettability – SnPb and lead free, Abstract retrieved from May 12, 2015, from www.umel.feec.vutbr.cz/~szend/novinky/wettability.pdf. [54] C. Odegard, C. Lambert, Comparative TDR Analysis as a Packaging FA Tool, Proceedings of the 25th International Symposium for Testing and Failure Analysis, ASM International, Materials Park, OH. November, 1999. pp. 49-55. [55] M. Hillert, Diffusion and interface control of reactions in alloys, MTA, 6 (1975) 5-19. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17963 | - |
dc.description.abstract | 為追求更細微的封裝方式,第一層次封裝漸漸由打線接合轉變為較高階的覆晶接合,並隨矽穿孔技術成熟,衍生出3D IC封裝技術,此一議題逐漸受到關注。欲於覆晶接合技術上取得突破,勢必從凸塊的製程與材料選擇著手進行改良,傳統採用銅凸塊或金凸塊,實際封裝情況由於銅較硬,應用於low k晶片時容易造成晶片破裂,並且在熱壓封裝時會遭遇共平面問題而使接點失效,致使良率降低,同時,銅凸塊的電鍍製程不穩定,電鍍廢液常造成環境汙染;而金凸塊則是會與銲錫快速反應,造成金脆現象,使接點失效。綜合以上問題,使此兩種凸塊不為覆晶組裝製程所喜。
本研究乃是評估銀合金凸塊的適用性,首先比較銀合金與銅凸塊之間的物理性質,比較後顯示銀合金凸塊硬度較軟,熱壓組裝接合製程時能提供較大的塑性變形量,除解決銅凸塊會發生的共平面問題外,也由於質地較軟,可用較小的力道在晶片上製作凸塊,因此適用於low k晶片而不會使晶片破裂,且相對於金凸塊,銀合金與銲錫反應良好,介金屬成長速度適中,可使用銲錫組裝,因此保有可重工與自我對位的特性,同時此製程可使用打線機台製作銀合金凸塊,節省設備費的同時,也由於此凸塊的製作過程並不會產生、也不需要任何有毒物質,符合環保議題,因此評估為一高可靠度之合金凸塊。 本研究首先針對銲錫與銀合金的潤濕現象進行討論,凸塊若與銲錫有不易潤濕的性質,在組裝過程將造成無法迴銲接合的情況,為了解此一現象是否影響銀合金凸塊的適用性,將銀合金、純銀、純銅與純金作潤濕天平測試,由結果得知,銀合金加入貴金屬(金、鈀)後,潤濕性相較於純銀顯著上升,接近純金,最差的是銅,潤濕度由最好至最差的順序為:純金 > 銀合金 > 純銀 > 純銅。 隨後進行銀合金凸塊與銲錫界面成長分析,過去使用的銅與純金凸塊,銅凸塊會在界面生成Cu3Sn與Cu6Sn5,但此介金屬層容易脆裂,造成晶片接點界面失效;金凸塊與銲錫則由於金容易快速擴散到錫的基底形成AuSn4、AuSn2、AuSn,即所謂金脆現象,只能採用導電膠組裝。為徹底了解銀合金凸塊與銲錫間的接合情形,選擇純銀、Ag-2Pd、Ag-4Pd三種材料與SAC305銲錫做迴銲以模擬銀合金凸塊與銲錫的界面反應,並於後續分別進行100℃、125℃、150℃、175℃、200℃與100小時、300小時、500小時、1000小時的高溫時效處理,結果顯示銀合金與銲錫反應良好,可觀察到連續的扇貝形界面,是為穩定的Ag3Sn介金屬,相較於金凸塊在同樣的迴銲條件下介金屬成長速度適中,厚度都在10μm以下,確保晶片的接合效果的同時,又不會過度成長造成接點界面脆化失效,並且,時效處理後發現介金屬成長很慢,不會有銀原子大量擴散到銲錫基底的現象發生,並且,時效處理後也不會如銅/錫界面一樣出現Kirkendall void或裂痕,雖在200℃的時效處理時Pd原子會越過Ag3Sn介金屬與Sn結合形成PdSn4,但其介金屬厚度仍遠低於金凸塊與銲錫的接合界面,而能維持銲球接點的強度。綜合上述優點,評估銀合金為一良好的覆晶組裝凸塊材料。 | zh_TW |
dc.description.abstract | The pursuit of fine pin and precisely electronic package demand of developing trend lead first level packaging evolving wire bonding into flip chip packaging. Due to the progress of TSVs technology, 3D IC technology becomes a remarkable issue of our semiconductor industry. To make a breakthrough advance on flip chip technology, we have to choose a proper material of flip chip bump and make improvement of its manufacture process. Traditionally we use gold and copper bump. In real case, due to its hardness property, copper bumps may cause fracture on low k chip during its manufacturing process. In thermal compression bonding, due to its low yield of plastic deformation, coplanar issue may occur. As for the gold bump, gold atom will diffuse into solder base quickly and form AuSnx intermetallic compound causing gold embrittlement issue. According to the above problems, these two kinds of materials are not good candidates for flip chip bumps.
Therefore, a newly developing Ag alloy stud bump is introduced. First we examine the hardness of Ag alloy. Experimental result shows that according to its low hardness, it can provide enough plastic deformation to suit the thermal compression bonding. Owing to Ag alloy’s soft property, we can use less strength to fabricate on low k chip process without causing fracture and crack. Furthermore, its interfacial reaction with solder is stable and good, remains reworkable and self-alignment property. At the same time its manufacture process has no pollution issues. To sum up, we expect Ag alloy as a good candidate with high reliability for stud bump. In this research, first part begins with its wettability discussion. If the material we choose doesn’t have well wetting phenomenon with solder, it won’t be able to assemble during flip chip process. In order to know the wettability, we tested pure gold, pure silver, pure copper and Ag alloy with SAC305 solder by wetting balance experiment. It shows that Ag alloy has good wettability which is near Au, due to the addition of Palladium and Gold. The wettability trend is: pure gold > Ag alloy > pure silver > pure copper. Next we decided to test the Ag alloy with SAC305 solder interfacial reaction properties. Flip chip industry used copper and gold bump in the past time. In copper’s case, it will form Cu3Sn and Cu6Sn5 intermetallic compound. But these two kinds of intermetallic compound is so fragile that it leads to weak bonding issue and forms Kirkendall void and crack after long time aging, reveals itself is not a good choose. As for the gold bump, due to the high diffusion coefficient between gold and solder, gold-embrittlement may occur, damage the interfacial texture. On the other hand, we tested pure Ag, Ag-2Pd, and Ag-4Pd reflowed with SAC305 solder under same condition. Ag alloy forms Scallop-shaped intermetallic compound, which is, Ag3Sn with proper thickness and well interfacial texture. Then we examine its property and reliability with high temperature aging test, under 100℃, 125℃, 150℃, 175℃, 200℃ and 100hr, 300hr, 500hr, 1000hr conditions. The result shows that it only forms Ag3Sn intermetallic compound and grows smoothly and slowly after aging without diffusing into solder base. Comparing to gold case, no Kirkendall voids or cracks formed. However, after aging under 200℃ for a long period of time, Pd forms PdSn4 with Sn. Though it thicken the IMC layer and results some minor cracks, but it still better than the gold and copper ones. Owing to these excellent behaviors, the Ag alloy stud bumps have the potential to replace the traditional copper and gold bumps. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:47:12Z (GMT). No. of bitstreams: 1 ntu-104-R02527066-1.pdf: 14178684 bytes, checksum: a0457b083e413fcd53f7169d9bd4bc76 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 審定書………………………………………………………………………I
誌謝………….…………………………………………………………….II 摘要……………………………...………………….………………………i Abstract………………………..………….……………………………….iii 目錄………………………………………………………………….……..v 圖目錄…………………………………………………...……………….viii 表目錄……………………………………………………………………xiv 第一章 前言 1 1-1 研究背景 1 1.2研究動機 3 1-3 研究目的 4 第二章 文獻回顧 8 2-1 電子構裝發展概論 8 2-2 覆晶接合 10 2-3 覆晶凸塊製程 14 2-4 Stud Bump 應用及發展 20 2-5 界面性質與介金屬反應 30 2-5-1 Ag-Sn系統 31 2-5-2 Pd-Sn系統 36 2-5-3 界面反應之潤濕現象 43 2-6 界面反應動力學 46 2-6-1 界面控制反應 47 2-6-2 擴散控制反應 48 第三章 實驗方法與步驟 49 3-1 凸塊潤濕性測試 49 3-2 奈米微硬度測試與維氏硬度測試 53 3-3 Stud Bump 界面反應 55 3-3-1 銀合金線材製作 55 3-3-2 Stud Bump模擬接合界面試片製作 55 第四章 實驗結果與討論 55 4-1 凸塊潤濕性質研究 61 4-2 銀合金凸塊與傳統銅凸塊機械性質研究 66 4-3 Stud Bump界面 69 4-3-1 純銀Stud Bump界面 73 4-3-2 銀合金Stud Bump界面 78 4-4 介金屬層厚度與動力學分析 93 第五章 結論 99 參考文獻 100 | |
dc.language.iso | zh-TW | |
dc.title | 覆晶組裝銀合金銲球凸塊界面反應研究 | zh_TW |
dc.title | Study on the Interfacial Reactions of Ag-alloy Stud Bumps for Flip-Chip Assembly | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張世穎,曹龍泉,王璽清 | |
dc.subject.keyword | 銀合金線,潤濕性,銲球凸塊,銲錫,介金屬, | zh_TW |
dc.subject.keyword | Ag alloy wire,Ag alloy stud bump,wettability,Solder,Intermetallic compounds, | en |
dc.relation.page | 106 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-07-27 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
顯示於系所單位: | 材料科學與工程學系 |
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