請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17962
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Chan-Hsiang Weng | en |
dc.contributor.author | 翁展翔 | zh_TW |
dc.date.accessioned | 2021-06-08T00:47:11Z | - |
dc.date.copyright | 2015-07-29 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-07-27 | |
dc.identifier.citation | [1] B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, and J. Craninckx, “A 70 dB DR 10 b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range,” IEEE J. of Solid-State Circuits, vol. 49, no. 5, pp. 1173-1183, May 2014.
[2] T. Takuji Miki, T. Morie, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, and S. Dosho, “A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement,” IEEE J. of Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, May 2015. [3] Y. Zhu, C.-H. Chan, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation,” IEEE J. of Solid-State Circuits, vol. 47, no. 11, pp. 2614-2626, Nov. 2012. [4] C.-J. Tseng, H.-W. Chen, W.-T. Shen, Wei-Chih Cheng, and Hsin-Shu Chen, “A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC” IEEE J. of Solid-State Circuits, vol. 47, no. 6, pp. 1334-1343, Jun. 2012. [5] C. C. Lee, and M. P. Flynn, “A SAR-assisted two-stage pipeline ADC,” IEEE J. of Solid-State Circuits, vol. 46, no. 4, pp. 859- 869, Jun. 2012. [6] D. Gubbins, B. Lee, P. K. Hanumolu, and U.-K. Moon, “Continuous-time input pipeline ADCs,” IEEE J. of Solid-State Circuits, vol. 45, no. 8, pp. 1456- 1468, Aug. 2010. [7] R. S. Rajan and S. Pavan, “Design techniques for continuous-time ΔΣ modulators with embedded active filtering,” IEEE J. of Solid-State Circuits, vol. 49, no. 10, pp. 2187- 2198, Oct. 2014. [8] M. Andersson, M. Anderson, L. Sundstrom, S. Mattisson, and P. Andreani, “A filtering ΔΣ ADC for LTE and beyond” IEEE J. of Solid-State Circuits, vol. 49, no. 7, pp. 1535-1547, Jul. 2014. [9] J. Greenberg, F. De Bernardinis, C. Tinella, A. Milani, J. Pan, P. Uggetti, M. Sosio, S. Dai, S. E.-S. Tang, G. Cesura, G. Gandolfi, V. Colonna, and R. Castello, “A 40-MHz-to-1-GHz fully integrated multistandard silicon tuner in 80-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 48, no. 11, pp. 2746 - 2760, Nov. 2013. [10] B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, J. Craninckx, “A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 470-471. [11] F. van der Goes, C. Ward, S. Astgimath1, H. Yan, J. Riley, J. Mulder, S. Wang and K. Bult, “A 1.5mW 68dB-SNDR 80MS/s 2-times interleaved SAR-assisted pipelined ADC in 28nm CMOS” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 200-201. [12] Y. Dong, R. Schreier, W. Yang, S. Korrapati, and A. Sheikholeslami, “A 235mW CT 0-3 MASH ADC achieving ?167dBFS/Hz NSD with 53MHz BW,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 480 - 481. [13] H. Chae, J. Jeong, G. Manganaro,and M. P. Flynn, “A 12 mW low power continuous-time bandpass ΔΣ Modulator with 58 dB SNDR and 24 MHz bandwidth at 200 MHz IF,” IEEE J. of Solid-State Circuits, vol. 49, no. 2, pp. 405- 415, Feb. 2014. [14] C.-Y. Ho, W.-S. Chan, Y.-Y. Lin, and T.-H. Lin, “A quadrature bandpass continuous-time delta-sigma modulator for a Tri-Mode GSM-EDGE/UMTS/ DVB-T Receiver,” IEEE J. of Solid-State Circuits, vol. 46, no. 11, pp. 2571- 2582, Nov. 2011. [15] S. Pavan, “Systematic design centering of continuous time oversampling converters,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 158-162, Apr. 2010. [16] S. Pavan, and P. Sankar, “Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique,” IEEE J. of Solid-State Circuits, vol. 45, no. 7, pp. 1365- 1379, Jul. 2010. [17] P. Shettigar and S. Pavan, “Design techniques for wideband single-bit continuous-time modulators with FIR feedback DACs,” IEEE J. of Solid-State Circuits, vol. 50, no. 9, pp. 518-530, Sep. 2003. [18] B. Putter, “ΣΔ ADC with finite impulse response feedback DAC,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 76-77. [19] O. Oliaei, “Sigma-delta modulator with spectrally shaped feedback,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 158-162, Apr. 2010. [20] O. Rajaee and U. Moon, “A 12-ENOB 6X-OSR noise-shaped pipelined ADC utilizing a 9-bit linear front-end,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2011, pp. 34-35. [21] S. Gupta, Yi Tang, D. J. Allstot, and J. Paramesh “Hybrid modeling techniques for low OSR cascade continuous-Time ΣΔ modulators,” in Proc. IEEE ISCAS, May 2008, pp. 2414-2417. [22] T. C. Caldwell and D. A. Johns, “An 8th-order MASH delta-sigma with an OSR of 3,” in Proc. IEEE ESSCIRC, Sep. 2009, pp. 476 - 479. [23] L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, “A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS,” IEEE J. of Solid-State Circuits, vol. 40, no. 12, pp. 2416-2427, Dec. 2005. [24] S.-J. Huang and Yung-Yu Lin, “A 1.2 V 2 MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 172-173. [25] Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, P.-C. Chiu, “A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 268-269. [26] Chi-Lun Lo, Chen-Yen Ho, Hung-Chieh Tsai, Yu-Hsin Lin, “A 75.1dB SNDR 840MS/s CT ΔΣ Modulator with 30MHz Bandwidth and 46.4fJ/conv FOM in 55nm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2013, pp. 60-61. [27] J. G. Kauffman, P. Witte, M. Lehmann, J. Becker, Y. Manoli, and M. Ortmanns, “A 72 dB DR, CT ΔΣ modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz BW,” IEEE J. of Solid-State Circuits, vol. 49, no. 2, pp. 392-404, Feb. 2014. [28] J. A. Cherry and W. M. Snelgrove, “Excess loop delay in continuous-time delta–sigma modulators,” IEEE Trans. Circuits and Syst. II, vol. 46, no. 4, pp. 376-389, Feb. 1999. [29] A. Das, R. Hezar, R. Byrd, G. Gomez and B. Haroun, “A 4th-order 86dB CT ΔΣ ADC with two amplifiers in 90nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 496-497. [30] T. Song, Z. Cao, and S. Yan, “A 2.7-mW 2-MHz continuous-time Σ∆ modulator with a hybrid active-passive loop filter,” IEEE J. of Solid-State Circuits, vol. 44, no.2, pp. 330-341, Feb. 2008. [31] K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho and A. Matsuzawa, “A fifth-order continuous-time delta-sigma modulator with single-opamp resonator,” IEEE J. of Solid-State Circuits, vol.45, no.4, pp. 697-706 Apr. 2010. [32] K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, Y. Tokunaga, S. Sakiyama and S. Dosho, “A 69.8 dB SNDR 3rd-order continuous time delta-sigma modulator with an ultimate low power tuning system for a worldwide digital TV-receiver,” IEEE Custom Integer. Circuits Conf., Sept. 2010 pp. 19-22. [33] K. Matsukawa, K. Obata, Y. Mitani, and S. Dosho, “A 10 MHz BW 50 fJ/conv. continuous-time ΔΣ modulator with high-order single opamp integrator using optimization-based design method,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2012, pp. 160-161. [34] R. Zanbaghi, P. K. Hanumolu and T. S. Fiez, “An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT modulator dissipating 13.7-mW,” IEEE J. of Solid-State Circuits, vol. 48, no.2, pp. 1-15, Feb. 2013. [35] M. Z. Straayer and M. H. Perrott, 'A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13μ CMOS,' IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 246-247. [36] M. Park and M. H. Perrott, 'A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time delta-sigma ADC with VCO-based integrator and quantizer implemented in 0.13 μm CMOS,' IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009. [37] K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, and P. K. Hanumolu, 'A 16-mW 78-dB SNDR 10-MHz BW CT ADC using residue-cancelling VCO-based quantizer,' IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2916-2927, Dec. 2012. [38] T. Oh, N. Maghari and U. Moon, 'A second-order ΔΣ ADC using noise-shaped two-step integrating quantizer,' IEEE J. of Solid-State Circuits, vol. 48, no. 6, pp. 1465-1474, June 2013. [39] M. Ranjbar, A. Mehrabi, O. Oliaei and F. Carrez, “A 3.1 mW continuous-time ΔΣ modulator with 5-bit successive approximation quantizer for WCDMA,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1479-1491, Aug. 2010. [40] H.-C. Tsai, C.-L. Lo, C.-Y. Ho and Y.-H. Lin, 'A 64-fJ/conv.-step continuous-time ΣΔ modulator in 40-nm CMOS using asynchronous SAR quantizer and digital ΔΣ truncator,' IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2637-2648, Nov. 2013. [41] V. Dhanasekaran, M. Gambhir, M. M. Elsayed, E. S.-Sinencio, J. S.-Martinez, C. Mishra, L. Chen and E. Pankratz, “A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 174-175. [42] O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu and U.-K. Moon, 'A 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline ADC,' IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2009, pp. 74-75. [43] M. S.-W. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-um CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. [44] M. Vadipour, C. Chen, A. Yazdi, M. Nariman, T. Li, P. Kilcoyne and H. Darabi, “A 2.1mW/3.2mW delay-compensated GSM/WCDMA sigma-delta analog-digital converter,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2008, pp. 180-181. [45] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns and Y. Manoli, 'A comparative study on excess-loop-delay compensation techniques for continuous-time sigma-delta modulators' IEEE Trans. Circuits and Systs. I, Reg. Papers, vol. 55, no. 11, pp. 3480-3487, Dec. 2008. [46] M. Ranjbar and O. Oliaei, “A multibit dual-feedback CT ΔΣ modulator with lowpass signal transfer function,” IEEE Trans. Circuits and Systs. I, Reg. Papers, vol. 58, no. 9, pp. 2083-2095, Sept. 2011. [47] W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun and Dave Ribner, “A 100 mW 10-MHz BW CT SD modulator with 87 dB DR and 91 dBc IMD,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 498-499. [48] C.-C. Lin, C.-H. Weng, T.-A. Wei, Y.-Y. Lin and T.-H. Lin, 'A TDC-based two-step quantizer with swapper technique for a multibit continuous-time delta-sigma modulator,' IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 61, no. 2, pp. 75-79, Feb. 2014. [49] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue and E. Romani, “A 20 mW 640 MHz CMOS continuous-time ADC with 20 MHz signal bandwidth, 80 dB dynamic range and 12 bit ENOB,” IEEE J. of Solid-State Circuits, vol. 41, no. 12, pp. 2641-2649, Dec. 2006. [50] P. Shettigar and S. Pavan, “Design techniques for wideband single-bit continuous-time modulators with FIR feedback DACs,” IEEE J. of Solid-State Circuits, vol. 47, no. 12, pp. 2865-2879, Dec. 2012. [51] M. Taherzadeh-Sani and A. A. Hamoui, “A 1-V process-insensitive current-scalable two-stage opamp with enhanced DC gain and settling behavior in 65-nm digital CMOS,” IEEE J. of Solid-State Circuits, vol. 46, no. 3, pp. 660-668, Mar. 2011. [52] John G. Kauffman, Pascal Witte, Joachim Becker and Maurits Ortmanns, “An 8.5 mW continuous-time ΣΔ modulator with 25 MHz bandwidth using digital background DAC linearization to achieve 63.5 dB SNDR and 81 dB SFDR,” IEEE J. of Solid-State Circuits, vol. 46, no. 12, pp. 2869-2881, Mar. 2011. [53] T. Caldwell, D. Alldred and Z. Li, “A reconfigurable ΔΣ ADC with up to 100 MHz bandwidth using flash reference shuffling,” IEEE Trans. Circuits and Systs. I, Reg. Papers, vol. 61, no. 8, pp. 2263-2271, Aug. 2014. [54] M. Andersson, M. Anderson, L. Sundstrom, S. Mattisson and P. Andreani, “A filtering ΔΣ ADC for LTE and beyond,” IEEE J. of Solid-State Circuits, vol. 49, no. 7, pp. 1-13, Jul. 2014. [55] M. Andersson, M. Anderson, L. Sundström, S. Mattisson, and P. Andreani, “A 9 MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression,” in Proc. IEEE ESSCIRC, Bucharest, Romania, Sep. 16-20, 2013, pp. 323-326. [56] M. Sosio, A. Liscidini, R. Castello, and F. D. Bernardinis, “A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC,” in Proc. IEEE ESSCIRC, Helsinki, Finland, Sep. 12-16, 2011, pp. 391-394. [57] C.-Y. Ho, C. Liu, C.-L. Lo, H.-C. Tsai, T.-C. Wang, Yu-Hsin Lin, “A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 174-175. [58] H. Chae, J. Jeong, G. Manganaro, M. Flynn, “A 12mW low-power continuous-time bandpass modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 148-149. [59] C.-H. Weng et al., “An 8.5MHz 67.2dB SNDR CTDSM with ELD Compensation Embedded Twin-T SAB and Circular TDC-based Quantizer in 90nm CMOS” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2014, pp. 106-107. [60] D.-H. Lee and T.-H. Kuo, “Advancing data weighted averaging technique for multi-bit sigma-delta modulators,” IEEE Trans. Circuits and Syst. II, vol. 54, no. 10, pp. 838- 842, Oct. 2007. [61] T.-H. Kuo, K.-D. Chen, and H.-R. Yeng, “A wideband CMOS sigma-delta modulator with incremental data weighted averaging” IEEE J. of Solid-State Circuits, vol. 37, no. 1, pp. 11-17, Jan. 2002. [62] K. Reddy, S. Dey, S. Rao, B. Young, P. Prabha, P. K. Hanumolu, “A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-Based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2015, pp. 256-257. [63] A. Sanya1, K Ragab, L. Chen, T. R. Viswanathan, S. Yan and Nan Sun, “A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping,” IEEE Custom Integer. Circuits Conf., Sept. 2014 pp. 1-4. [64] B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand, and P. K. Hanumolu, “A 75dB DR 50MHz BW 3rd Order CT-ΔΣ Modulator Using VCO-Based Integrators,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2014, pp. 81-82. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17962 | - |
dc.description.abstract | 本論文以設計高效能連續時間三角積分調變器為目標,針對調變器的迴路濾波器架構、量化器架構以及回授路徑線性度的校正電路,提出了改善的方法。論文第一部份提出了使用單級運算放大器濾波器以及時域量化器的架構,實現了一個低功耗連續時間三角積分調變器,所提出的迴路濾波器架構使用了一個運算放大器以及改進過的雙T型被動回授網路,達到二階共振功能以及前饋路徑。搭配提出的雙T型被動回授網路,並且透過適當的選取回授路徑的注入點,可以在不增加額外的硬體下,就可以達成延遲迴路補償。
此外,為了降低量化器的功率消耗並且同時解決回授數位類比轉換器的線性度問題,本論文提出了一個內建動態元件匹配功能的時域量化器,取代原先一般調變器常用的快閃式量化器以及用於校正回授路徑線性度的動態元件匹配電路,所提出的時域量化器可以同時達到量化迴路濾波器的輸出以及線性化回授數位類比轉換器的目的。 論文第二部份則是基於第一個設計,更近一步將雙步階的概念應用於時域量化器,降低時域量化器的功耗以及硬體面積,為了更進一步增加信號頻寬,論文第三部份的設計是使用兩個運算放大各自搭配不同架構的雙T型網路,達到四階雜訊整形的功能,量化器方面則是採用內建隨機亂數加權平均電路之時域內插快閃式量化器來達到低功耗的訴求,並同時解決量化器以及回授路徑的線性度問題。 此論文中共實現了三個三角積分調變器,皆使用台積電90奈米互補式金氧半製程所實現,三個調變器分別操作於300MHz, 256MHz以及320MHz的取樣頻率,在8.5MHz, 8MHz和13MHz的信號頻寬下,最大可以達到67.2 dB, 69.6 dB, 68.1 dB 的訊號雜訊比。 | zh_TW |
dc.description.abstract | To achieve highly energy-efficient designs of continuous-time delta-sigma modulators (CTDSMs), the thesis proposes several new techniques and applies those to the loop filter, quantizer and linearization circuits used in the feedback DAC. In the first part of the thesis, a power-efficient CTDSM employing a single-amplifier biquad (SAB)-based loop filter topology and a time-domain quantizer is proposed. With single amplifier and the modified twin-T passive feedback network, the proposed SAB-based loop filter can achieve 2nd-order resonating function and feedforward path concurrently. By choosing the feedback node properly, the excess loop delay compensation path can be realized without additional hardware. Meanwhile, to resolve the nonlinearity issue of feedback DAC and lower the power consumption of the quanitzer, a time-domain quantizer embedded with data-weighted-averaging (DWA) function is proposed to replace a flash-type quantizer and DWA shuffling logics. The proposed quantizer can digitize the analog output signal of the loop filter and linearize the feedback digital-to-analog converter concurrently. Based on the first design, the second part of the thesis proposed a CTDSM employing a 2-step time-domain quantizer to further reduce the power consumption and hardware cost. In the third part of the thesis, the CTDSM adopted two SAB-baed filters with two different T networks to achieve the 4th-order noise shaping. A flash-type quantizer with the interpolating technique is used to digitize output of the loop filter. Furthermore, a random-skipped incremental data weighted averaging (RS-IDWA) function is proposed to address the linearity issue of quantizer and feedback DAC.
Fabricated in 90-nm CMOS and operated at 300MHz, 256MHz and 320MHz, the proposed CTDSMs can achieve peak SNDR of 67.2 dB, 69.6 dB, and 68.1 dB over a 8.5 MHz, 8 MHz and 13 MHz signal bandwidth, respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:47:11Z (GMT). No. of bitstreams: 1 ntu-104-D98943003-1.pdf: 2983024 bytes, checksum: 5c41fd05ddb9fbcc6468f7431d8ba05f (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | CHAPTER 1. INTRODUCTION 1
1.1 INTRODUCTION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2. BASIC UNDERSTANDING OF CTDSM 5 2.1 DELTA-SIGMA MODULATOR ARCHITECTURE (DSM) 5 2.1.1 SAMPLING AND QUANTIZATION 6 2.1.2 OVERSAMPLING 9 2.1.3 NOISE SHAPING TECHNIQUE 11 2.2 LOOP FILTER TOPOLOGIES 14 2.2.1 FEED-FORWARD LOOP FILTER CTDSM TOPOLOGY 14 2.2.2 FEED-BACK LOOP FILTER TOPOLOGY 16 2.2.3 HYBRID FEED-FORWARD AND FEED-BACK LOOP FILTER 19 2.3 COMPARISON AMONG CTDSMS WITH FEED-FORWARD, FEED-BACK AND HYBRID LOOP FILTERS 21 2.4 NON-IDEAL EFFECTS IN CONTINUOUS-TIME DELTA-SIGMA MODULATOR 24 2.4.1 MISMATCH ISSUE IN A MULTI-BIT FEEDBACK DAC AND DWA FUNCTION 24 2.4.2 EXCESS LOOP DELAY (ELD) 29 2.4.3 FINITE GAIN BANDWIDTH OF INTEGRATOR 31 CHAPTER 3. CTDSM FOR WIRELESS RECEIVERS 35 3.1 RESEARCH MOTIVATION 35 3.2 MODULATOR ARCHITECTURE 39 3.3 DESIGN CONSIDERATIONS 44 3.4 COMPARISON 47 CHAPTER 4. CIRCUIT IMPLEMENTATION 53 4.1 ARCHITECTURE OF THE PROPOSED MODULATOR 53 4.2 OPERATIONAL AMPLIFIER 53 4.3 TIME-BASED QUANTIZER - VTC AND CRTDC 56 4.4 DAC CIRCUIT 62 4.5 SIMULATION RESULTS 65 CHAPTER 5. EXPERIMENTAL RESULT & BRIEF CONCLUSION 67 5.1 TEST SETUP 67 5.2 EXPERIMENTAL RESULTS AND COMPARISON 68 CHAPTER 6. TIME-DOMAIN TWO-STEP QUANTIZER & EXPERIMENTAL RESULTS 75 6.1 TWO-STEP QUANTIZER 75 6.2 CIRCUIT IMPLEMENTATIONS OF OVERALL MODULATOR 77 6.3 SIMULATION RESULTS 78 6.4 EXPERIMENTAL RESULTS AND COMPARISON 80 CHAPTER 7. A 4TH-ORDER CTDSM WITH INTERPOLATING FLASH QUANTIZER AND RANDOM-SKIP DWA FUNCTION 87 7.1 MODULATOR ARCHITECTURE 87 7.2 DESIGN CONSIDERATIONS 95 7.3 CIRCUIT DETAILS OF PROPOSED 4TH-ORDER MODULATOR 96 7.3.1 OPERATIONAL AMPLIFIER 97 7.3.2 DAC CIRCUIT 98 7.3.3 INTERPOLATING QUANTIZER & RS-IDWA 101 7.4 EXPERIMENTAL RESULTS AND COMPARISON 110 CHAPTER 8. CONCLUSIONS AND FUTURE WORK 117 8.1 CONCLUSIONS 117 8.2 FURTHER WORK 119 REFERENCES 121 | |
dc.language.iso | en | |
dc.title | 高效能連續時間三角積分調變器之設計 | zh_TW |
dc.title | Design of Highly Energy-Efficient Continuous-Time Delta-Sigma Modulators | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),郭泰豪(Tai-Haur Kuo),謝志成(Chih-Cheng Hsieh),蔡宗亨(Tsung-Heng Tsai),許雲翔(Yun-Shiang Shu) | |
dc.subject.keyword | 三角積分調變器,類比數位轉換器,時域量化器,加權平均,隨機亂數加權平均,延遲迴路補償,單級雙階濾波器, | zh_TW |
dc.subject.keyword | delta-sigma modulator,analog to digital converter,time-domain quantizer,data weighted averaging,random-skipped data weighted averaging,excess loop delay,single amplifier biquad, | en |
dc.relation.page | 127 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-07-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-104-1.pdf 目前未授權公開取用 | 2.91 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。