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標題: | 超高畫質高效能視訊編碼器晶片之演算法及架構設計 Algorithm and Architecture Design of Bandwidth Efficient HEVC Encoder for 8K UHDTV Applications |
作者: | Sung-Fang Tsai 蔡松芳 |
指導教授: | 陳良基(Liang-Gee Chen) |
關鍵字: | 視訊編碼,超高畫質,高效能視訊編碼,編碼器, Video encoding,UHDTV,H.265,HEVC,encoder,chip, |
出版年 : | 2013 |
學位: | 博士 |
摘要: | 視訊日益廣泛地運用在各種不同的應用情境中。以網路頻寬而言,預計2014年九成的網際網路頻寬都將用來傳遞視訊信號。為了求得更真實的廣視角體驗,未來視訊解析度的要求也將提升到7680x4320p的超高視覺(SHV)解析度。在此超高解析度下,目前的H.264/AVC視訊壓縮技術將無法提供足夠的壓縮率。次世代的高效能影像壓縮標準(HEVC)將比前一代的H.264/AVC高出52%的壓縮能力,足夠提供4320p的壓縮能力。然而,其對於記憶體頻寬的要求與複雜度均大幅提高,需要有新的硬體架構設計法則。
在本篇論文中,我們提出了一單晶片HEVC視訊編碼器的硬體設計,我們針對記憶體頻寬與複雜度,提出了高複雜度的模式決定演算法,3層記憶體階層架構,以及畫面層級過濾流程。此視訊編碼器最高能提供8192x4320p畫素的即時每秒30張的編碼能力,使用28奈米製程製作,總面積為25mm2 , 8350K等效邏輯閘。比較之前所提出針對H.264設計的系統,在同樣的品質下,我們所提出的系統可節省62%的頻寬。 Video is increasingly used in a wide variety of applications. In the future, more than 90% of internet traffic will be video in 2014. While the bandwidth-consuming video is more and more used, resolution requirement on the other hand is going up to 8K UHDTV/SHV, making bandwidth a serious problem. To support such high resolution video for mass usage, video compression is very important. The next generation standard H.265/HEVC provides more than 50% compression rate compared with H.264/AVC, enabling 4K/8K UHDTV applications. However, the bandwidth and complexity problem of H.265/HEVC at UHDTV poses new challenges to video codec designers. These problem needs to be solved and least amount of quality loss should expose. In this dissertation, we proposed a single-chip bandwidth efficient H.265/HEVC encoder that supports real-time encoding of 8192x4320p at 30fps. Proposed low-cost high complexity mode decision hardware architecture supports complex prediction modes in H.265/HEVC. For loop filtering, we proposes some hardware-oriented hardware architecture that supports non-deblocking loop filtering efficiently. In addition, 3-level memory architecture supports huge bandwidth requirement for motion estimation. At system level, bandwidth-efficient frame-level pipeline is proposed and saves extra bandwidth. The proposed system is also implemented in chip. The core size of the chip is 25mm^2 which contains 8350K gates with 7.55MB on-chip SRAM using 28nm CMOS Technology. The coding gain is over 62% above all the previous work, and bandwidth efficiency is also highest. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17671 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-102-1.pdf 目前未授權公開取用 | 14.24 MB | Adobe PDF |
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