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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17618Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Chin-Huang Huang | en |
| dc.contributor.author | 黃金煌 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:25:41Z | - |
| dc.date.copyright | 2013-07-19 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-15 | |
| dc.identifier.citation | [1] J.B. Kuo, J. Lou, 'Low-Voltage CMOS VLSI Circuits,' Wiley, New York,1999.
[2] S. Chou, “Integration and innovation in the nanoelectronics era,” IEEE International Solid-State Circuits Conference, vol. 1, pp. 36-41, Feb. 2005. [3] G .E. Moore, 'Progress in Digital Integrated Electronics,' International Electron Devices Meeting, Vol. 21, pp. 11-13, 1975. [4] ITRS, 'ITRS 2004 Update Documents for Review,' http://www.itrs.net/Links/2004Update/2004Update.htm. [5] A. Bellaouar, M. I. Elmasry,“Low-Power Digital VLSI Design：Circuits and System,”Kluwer,1996. [6] ITRS,“ITRS 2001 Documents for Review,” http://www.itrs.net/Links/2001UTRS/Home.htm [7] Power Modeling and Leakage Reduction, 'http://eda.ee.ucla.edu/ EE201A-04Spring/leakage~pres.ppt' [8] T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchiya, “A 0.5V MTCMOS/SIMOX Logic Gate,” IEEE J. Solid-State Circuits, Vol. 32, No. 10, pp. 1604-1609, 1997. [9] S. Shigematsu, S. Muthoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,” IEEE J. Solid-State Circuits, Vol. 32, No. 6, pp. 861-869, 1997. [10] Micro Electronics, ' Low-power embedded design trends' http://www.mem.com.tw/article_content.asp?sn=0805020016 [11] Harry I-An Chen 'Triple-threshold static power minimization technique in high-level synthesis using 90nm MTCMOS technology' [12] Global Source 'Static Timing Analysis' http://bbs.ednchina.com/BLOG_ARTICLE_168381.HTM [13] 'Power Compiler User Guide,'2007,03. [14] S. Mukhopadhyay, K. Roy, 'Leakage Estimation and Leakage Control for Nano-Scale CMOS Circuits,' Design Automation Conference, 2004. [15] J.B. Kuo, 'CMOS Digital IC,' McGraw-Hill, Taiwan, 1996. [16] R.X. Gu, M.I. Elmasry, 'Power dissipation analysis and optimization of deep submicron CMOS digital circuits,' IEEE Journal of Solid-stateCircuits, Vol. 31, Issue 5, pp. 707-71 3, May 1996. [17] SMIC Synopsys 'Reference Flow' http://www.smics.com/eng/design/reference_flows10.php [18] SMIC Cadence 'Reference Flow' http://www.smics.com/eng/design/reference_flows16.php [19] Cadence FAB mixed-signal foundry experts 'Cadence Reference Flow' http://www.xfab.com/en/service/design-support/eda-partners/cadence [20] Cadence, ' Encounter dmsflow User Guide,' ~2005.12. [21] Cadence, ' Encounter User Guide,' ~2005.12. [22] Cadence, ' Encounter fetxtcmdref User Guide,' ~2007.03 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17618 | - |
| dc.description.abstract | 這篇論文主要是在利用MTCMOS技術透過EDA工具來對晶片Layout來做優化。第一章首先介紹近年來互補式金氧半的發展演進，第二章開始介紹MTCMOS技術與其應用，接下來是電子設計自動化技術在晶片積體電路設計中的應用，包含電路中的功率消耗分析和時序分析。第三章則是介紹使用MTCMOS的優化方法來對晶片做功率消耗分析，針對我們使用的兩種不同的MTCMOS演算法來做比較，最後在對優化過後的晶片做重新擺放來解決熱點叢聚的問題。第四章為結論和未來研究方向。 | zh_TW |
| dc.description.abstract | This thesis presents the method of using the MTCMOS technology to optimize the SOC chip considering layout via EDA tools. Chapter 1 presents the recent CMOS VLSI SOC design circuit trend. Then Chapter 2 describes MTCMOS technology and its applications. The application of electronic design automation in SOC circuits is presented, including the power consumption analysis and timing analysis. Chapter 3 presents the method of power consumption analysis of the low power SOC chip using MTCMOS technology. Two MTCMOS algorithms are presented for compared. At last a procedure of placement is performed on an SOC chip to solve the problem of clustering hotspots. Chapter 4 is the conclusion and future work. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:25:41Z (GMT). No. of bitstreams: 1 ntu-102-R00943160-1.pdf: 2037877 bytes, checksum: 291ca248119ed1054fef271576da73e3 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 致謝 iii
中文摘要 iv ABSTRACT v 目錄 vi 圖目錄 viii Chapter 1 導論 1 1. 1 矽互補式金氧半超大型積體電路的演化與發展趨勢 1 1. 2 研究目標與論文架構 7 Chapter 2 多重臨界電壓系統電路分析 8 2. 1 低功耗嵌入式設計風潮 8 2. 2 多重臨界電壓技術 10 2. 3 雙臨界電壓技術(DUAL-THRESHOLD TECHNIQUE) 12 2. 4 EDA TOOL簡介 13 2. 5 數位積體電路設計中EDA技術 16 2. 6 靜態時序分析(STATIC TIMING ANALYSIS) 20 2. 7 晶片系統功率消耗分析 26 2. 8 結論 29 Chapter 3 使用電子設計自動化技術設計雙臨界電壓技術低功率系統晶片應用 30 3. 1 從GATE LEVEL NETLIST到自動繞線佈局 30 3. 2 邏輯閘佈局以及繞線 32 3. 3 晶片功率消耗分析 35 3. 4 晶片功率消耗優化 37 3. 5晶片優化後重新邏輯閘佈局 51 3. 6 結論 64 Chapter 4 結論與未來研究方向 65 參考文獻 67 | |
| dc.language.iso | zh-TW | |
| dc.title | 利用MTCMOS技術實現低功率SOC系統晶片佈局最佳化 | zh_TW |
| dc.title | Layout Optimization Using MTCMOS Technique for Low-Power SOC Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳正雄,林吉聰,林浩雄,呂學士 | |
| dc.subject.keyword | 佈局最佳化, | zh_TW |
| dc.subject.keyword | MTCMOS, | en |
| dc.relation.page | 69 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-102-1.pdf Restricted Access | 1.99 MB | Adobe PDF |
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