請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17615完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Yi-Hsuan Su | en |
| dc.contributor.author | 蘇以煊 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:25:31Z | - |
| dc.date.copyright | 2013-08-07 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-15 | |
| dc.identifier.citation | [1] Semiconductor Industry Association, “International Technology Roadmap for
Semiconductors - 2012 Update”, 2012. http://www.itrs.net [2] K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics, “ Proc. Of IEEE, 85(4), 558-576, 1997. [3] J.Y. Choi, L.G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol.ED-38, p.1384, June 1991. [4] J.Y. Choi, R.Sundaresan, J.G. Fossum, “Monitoring Hot-electron-Induced Degradation of Floating-Body SOI MOSFET’s,” IEEE Electron Device Letters, Vol.11, p.156, April 1990. [5] J.P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Electron Device Letters, Vol.EDL-9, p.97, Feb. 1988. [6] J. Pretet, D. Ioannon, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs,” Sol. St. Elec., vol. 46, no. 11, pp. 1699-1707, 2002. [7] J. P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Electron Device Letters,Vol.EDL-9,p.97,Feb. 1988. [8] S.S.Chen and J.B.Kuo, “Analytical Kink Effect Model of PD SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, pp. 447-458, March 1997. [9] S.C.Lin and J.B.Kuo, “Temperature Dependent Kink Effect Model for PD SOI NMOS Devices,” IEEE Trans. Electron Devices, pp. 254-258, Feb. 1999 [10] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. [11] H. J. Hung, J. B. Kuo, D. Chen, C. T. Tsai an C. S. Yeh, ”Shallow TrenchIsolation-Related Narrow Channel Effect on the Kink Effect Behavior of 40nm PD SOI NMOS Device, ”Solid State Electronics, Vol. 54, No. 1, Jan. 2010 [12] K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEETrans.Electron Devices, Vol. 44, No. 2, pp. 324-330,Feb.1997. [13] YG Chen, JB Kuo, Z Yu, RW Dutton,’’An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices,’’ Solid-State Electronics, 1995 [14] J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gainmodel for BJT devices operating at 77 K,” Solid State Electron., vol. 35,no. 6, pp. 785–790, Jun. 1992. [15] K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice TemperatureModel for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEETrans.Electron Devices, Vol. 44, No. 2, pp. 324-330,Feb.1997. [16] S. W. Fang and J. B. Kuo, “Modeling the Floating-Body-Effect-Related Transient Behavior of 40nm PD SOI NMOS Device via the SPICE Bipolar/MOS Model” pp.1,2, 7-9 Dec. 2011 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17615 | - |
| dc.description.abstract | 本論文主要在研究一個考慮浮動基體效應的部分解離絕緣體上矽金氧半元件(PD SOI NMOS)，我們討論其背閘極偏壓效應(Back gate bias effect)對於部分解離絕緣體上矽N型元件(PD SOI NMOS)的關閉暫態影響。第一章我們介紹絕緣體上矽金氧半(PD SOI)元件以及其相關的特性和效應，並進一步對部分解離絕緣體上矽金氧半元件(PD SOI)做主要的探討。第二章則講解部分解離絕緣體上矽金氧半元件(PD SOI MOS)的電流傳導機制和浮動基體效應(Floating-body effect)所帶來的影響，然後介紹基礎的精簡電流模型以及基本的值流和元件關閉暫態分析。第三章我們把重點放在背閘極偏壓(back gate bias)對於元件直流及元件關閉暫態的影響，引入雙MOS架構的概念，進一步的考慮將背閘極偏壓(back gate bias)的電流模型做出修正。最後也利用二維模擬軟體 Medici來模擬元件直流及關閉暫態的行為來印證此修正行電流模型的精卻性。第四章為論文的總結與未來工作。 | zh_TW |
| dc.description.abstract | In this thesis, the transient analysis of partially depleted silicon-on-insulator (PD-SOI) NMOS devices considering back gate bias effect and floating-body effect is presented. Chapter 1 presents the introduction and special effects of PD-SOI NMOS devices. Chapter 2presentsthe current conduction mechanism and floating-body effect of PD-SOI NMOS devices. Then, we introduce the compact current model, DC analysis, and turn-off transient analysis on PD-SOI NMOS devices. In Chapter 3, we focus on the influence of back gate bias on DC and turn-off transient behaviors of PD-SOI NMOS devices. In addition, the concept of the MOS pair is introduced and the current model is modified considering back gate bias effect. At last, DC analysis and turn-off transient analysis are performed on the PD-SOI NMOS device by Medici, the 2-D simulation tool, to make sure that the modified model is correct. Chapter 4 is conclusions and future work. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:25:31Z (GMT). No. of bitstreams: 1 ntu-102-R00943157-1.pdf: 2796693 bytes, checksum: 87ae68d0014ba7391494b6ec78d2fe7b (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 致謝 i
中文摘要 ii Abstract iii 口試委員審定書 iv 目錄 v 圖目錄 vii Chapter 1導論 1 1.1絕緣體上矽金氧半元件(SOI)簡介 4 1.2部分解離以及完全解離絕緣體上矽金氧半元件 7 1.3總結與論文架構 10 Chapter 2 部分絕緣體上矽N型金氧半元件之基礎直流與暫態電流模型概論 11 2.1撞擊游離效應所帶來的影響 13 2.2暫態電流模型概論 20 2.3考慮寄生電容之電流精簡模型 22 2.4總結 27 Chapter 3 考慮背閘極偏壓之部份解離絕緣體上矽金氧半元件電流模型修正模 型以及下降暫態分析 28 3.1不同背閘極偏壓對於元件特性的影響 30 3.2考慮背閘極偏壓精簡電流模型修正 33 3.3暫態電流模型之修正 40 3.4總結 47 Chapter4總結與未來展望 48 REFERENCE 50 | |
| dc.language.iso | zh-TW | |
| dc.title | 考慮背閘極偏壓效應之部份解離絕緣體上矽
金氧半元件關閉暫態分析 | zh_TW |
| dc.title | Turn-off Analysis of Partially Depleted SOI
Device Considering Back Gate Bias Effect | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林浩雄,林吉聰,呂學士,陳正雄,葉正信 | |
| dc.subject.keyword | 絕緣體上矽,背閘極, | zh_TW |
| dc.subject.keyword | PDSOI,Back Gate Bias, | en |
| dc.relation.page | 52 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-102-1.pdf 未授權公開取用 | 2.73 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。