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標題: | 高遷移率p型鍺金氧半場效電晶體的製備與其低溫特性之模擬與量測 Fabrication and Characterization of High Mobility Ge p-MOSFETs |
作者: | Huang-Jhih Ciou 邱皇智 |
指導教授: | 劉致為 |
關鍵字: | 鍺,後閘極製程,高遷移率,鎳鍺化物,應變,金氧半場效電晶體, Germanium,Gate-Last Process,High Mobility,NiGe,Strain,MOSFET, |
出版年 : | 2013 |
學位: | 碩士 |
摘要: | 半導體工業跟隨著莫爾定律的規則,持續地將元件微縮化 (Scaling)。但傳統的矽金氧半場效電晶體(MOSFETs)技術已經逐漸達到其微縮的極限。為了要突破物理極限以維持著元件微縮的步調,必須要開發更高載子遷移率(Carrier Mobility)的新材料來取代傳統矽做為元件通道材料,因此近來鍺或是其他三五族的高載子遷移率材料受到相當的矚目,而其中又以擁有高電子與電洞高遷移率的鍺被視為能在未來使用於22奈米製程節點以下以取代矽。然而,鍺元件仍然存在著許多難題需要克服,例如高介電係數材料(High-κ)的製程整合,參雜物 (Dopants)的活化改善,表面鈍化的處理,以及適當的應變(Strain)技術。
本論文中,我們利用了高速熱氧化法(RTO)來成長二氧化鍺(GeO2)做為鍺與高介電系數材料的介面層(Interfacial Layer),接著使用了氧氣為基底的低溫原子沉積(ALD)來生長三氧化二鋁(Al2O3)來保護並增進二氧化鍺的品質,其效應可由鍺金氧半電容元件的電容特性量測得知。此外,我們用多重離子佈植增加摻雜的濃度且用了高速熱退火(RTA)來活化離子佈值,並使用鎳鍺化物 (Nickel-germanide) 來作為電極降低電效應而成功製作了高開關比率的p+/n二極體,其二極體的理想因子為1.01代表接面中的缺陷很少。 先前許多研究中的p型鍺金氧半元件大多專注於 (001) 基板上的金氧半場效電晶體。根據理計算,對於p型鍺通道電晶體而言,在(110)基板上的<110>通道方向擁有最高的載子遷移率,然而到目前為止關於(110)的p型鍺金氧半元件卻很少被研究。在本研究中,而我們利用了二氧化鍺使鍺的表面鈍化,以及使用高速熱退火來活化源極以及汲極的離子佈值區,成功的使高介電係數介電質與後閘極製程(gate-last)整合到鍺基板上,並在鍺的(110)基板上製作出了有高遷移率電洞的鍺金氧半場效電晶體元件。而對於元件加了適當的應力後,藉由產生鍺的能帶分裂(Band Splitting)以及電洞重新分佈(Hole Repopulation)可再使載子遷移率提升。 而為了進一步探討載子遷移率機制對溫度的變化,我們將元件在低溫之下量測探討其特性,接著再進一步的分析遷移率的變化以及在變溫之下臨界電壓的平移並提出一個理論模型以及模擬去解釋。 Recently, semiconductor industry has followed the path of scaling trend based on Moore’s law. But conventional bulk Si MOSFETs is approaching its fundamental scaling limits. To continually scale the device, high mobility materials have been comprehensively investigated as channel material for replacing Si, such as Ge or III-V material due to its high intrinsic carrier mobility. Ge has become a promising candidate for 22nm nodes beyond CMOS technology due to its compatibility of Si-based technology. However, there are several critical issues for Ge devices. The primary challenges to achieve high mobility Ge MOSFETs are the high-k integration process, the improvement of dopants activation, reduction of interface traps density, and proper strain configuration. In this thesis, rapid thermal oxidation (RTO) is used as the fast and effective Ge interface passivation. Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD) using molecular oxygen (O2) as oxidant at low temperature. The electrical characterizations by dispersion-free C-V curves of Ge MISCAPs are investigated. Moreover, high on/off ratio p+/n diodes were fabricated by two steps ion-implantation and rapid thermal annealing for activation. In addition, The NiGe contact is used to improve the contact resistance. The ideality factor of ~1.01 and high on/off ratio of ~105 are obtained, indicating low defects within the junction. In the previous work, (001) Ge p-MOSFETs have been reported. Mobility on (110) orientation with <110> channel direction has highest hole mobility [3]. However, there is few reports regarding (110) Ge p-MOSFETs. In this work, with GeO2 passivation, rapid thermal annealing on Source/Drain activation and gate-last integration process with high-κ dielectrics, Ge p-MOSFETs demonstrating high hole electron mobility (~ 528 cm2/V-s) for Ge (110) substrate and excellent electrical transistor behaviors are fabricated. Proper stress results in band splitting and hole repopulation which can further boost the mobility. To investigate the carrier scattering mechanisms, the device are measured at low temperature. The temperature dependence of mobility, S.S. and Vt are also studied by low temperature measurement. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17540 |
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顯示於系所單位: | 光電工程學研究所 |
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