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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 曹恆偉 | |
dc.contributor.author | Chung-Wei Huang | en |
dc.contributor.author | 黃仲瑋 | zh_TW |
dc.date.accessioned | 2021-06-08T00:18:55Z | - |
dc.date.copyright | 2013-08-09 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-07-26 | |
dc.identifier.citation | [1] M. Bossert, Channel Coding for Telecommunications, John Wiley & Sons, Inc. , 1999.
[2] S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications, Prentice-Hall, 1983. [3] S. B. Wicker and V. K. Bhargava, Reed-Solomon Codes and Their Applications, IEEE Press, 1994. [4] S. B. Wicker, Error control systems for digital communication and storage, Prentice Hall, 1995. [5] X. Chen , I. S. Reed, Error-Control Coding for Data Networks, Kluwer Academic Publishers, 1999. [6] A. Athavale, C. Christensen, “High-Speed Serial I/O Made Simple, A Designer’s Guide with FPGA Applications,” Preliminary Edition, Xilinx Connectivity Solutions, PN0402399, 2005. [7] A. Das, Digital Communication, Springer Berlin Heidelberg, 2010. [8] A. S. Tanenbaum, Computer Networks, Prentice Hall, 5th edition, 2010. [9] K. Mustafa, C. Sterzik, “DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CM,” Texas Instruments Application Report, 2003. [10] 高速串列通訊技術的發展、設計及應用 (http://www.eettaiwan.com/ART_8800344729_675327_TA_249b94e4.HTM) [11] A. Bateman, Digital Communications, WuNan, 2000. [12] 仇佩亮, 信息論與編碼, 北京高等教育出版社, 2003. [13] H. C. Chang, C. B. Shung, “A (208,192;8) Reed-Solomon decoder for DVD application,” IEEE International Conference, pp. 957-960,vol. 2, 1998. [14] S. Baron et al., Implementing the GBT data transmission protocol in FPGAs, in proceedings of Topical Workshop on Electronics for Particle Physics, September, 21–25, 2009 Paris, France. [15] Telecommunication Standardization Section, International Telecom. Union, “Forward Error Correction for Submarine Systems,” ITU, Geneva, Switzerland, ITU-T Recommendation G.975, Oct. 2000. [16] L. Song, M-L. Yu and M. S. Shaffer, “10 and 40-Gb/s Forward Error Correction Devices for Optical Communications,” IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1565-1573,Nov. 2002. [17] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen and I. S. Reed, “A VLSI Design of a Pipeline Reed-Solomon Decoder,” IEEE Trans. on Computers, vol. C-34, no.5, pp.393-403, May. 1985. [18] H. Lee, “High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder,” IEEE Trans. On VLSI Systems, vol. 11, no. 2, pp. 288-294, April. 2003. [19] H. Lee, “An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder,” IEEE Computer Society Annual Symposium on VLSI, pp. 209-210, Feb. 2003. [20] S. Lee, H. Lee, J. Shin and J. Ko ”A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed- Solomon Decoders,” IEEE International symposium on Circuits and System (ISCAS 2007), pp. 901-904, May 2007. [21] J. H. Baek and M. H. Sunwoo, “New Degree Computationless Modified Euclidean Algorithm and Architecture for Reed-Solomon Decoder,” IEEE Trans. on VLSI Systems, vol. 14, no. 8, pp 915-920, Aug. 2006. [22] 國家晶片系統設計中心, “混合訊號測試實驗室機台操作參考手冊”, 2009. [23] Xilinx DS100 Virtex-5 Family Overview. [24] Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide. [25] Xilinx UG347 ML505/ML506/ML507 Evaluation Platform, User Guide. [26] Xilinx UG204 LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard v1.7 Getting Started Guide. [27] Xilinx DS601 LogiCORE IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard v1.7. [28] 徐文波, 田耘, Xilinx FPGA開發實用教學, 佳魁資訊, 2013. [29] 何賓, Xilinx FPGA設計權威指南, 清華大學出版社, 2012. [30] 湯琦, 蔣軍敏, Xilinx FPGA高級設計及應用, 電子工業出版社, 2012. [31] A. S. Medina,D. Torres, and J. Hermosillo, “VLSI CONFIGURABLE FRAMER FOR SONET/SDH STS-3/STM-1,” Proc. of Iberchip IWS, Guadalajara, Mexico, 2002. [32] Tektronix, Synchronous Optical Network (SONET) Tutorial. [33] Xilinx DS512 Block Memory Generator v3.3. [34] Y. Fan, Z. Zilic, and M. Chiang, “A versatile high speed bit error rate testing scheme,” Proc. IEEE Int. Symp. Quality Electronic Design, 2004, pp. 395–400. [35] Agilent Technologies, 如何在N490xA/B串列BERT上量測位元錯誤率(BER)達要求的信心水準? (http://www.home.agilent.com/agilent/editorial.jspx?ckey=1481106&id=...&cc=TW&lc=cht) [36] G. P. Agrawal, Fiber-Optic Communication Systems, 3rd ed, Wiley, 2002. [37] H. Lee, “A VLSI Design of A High-Speed Reed-Solomon Decoder,” Proceedings of the 14th Annual IEEE International on ASIC/SOC Conference, pp.316-320, 12-15 Sept. 2001. [38] H. Lee, M. L. Yu, and L. Song, “VLSI Design of Reed-Solomon Decoder Architectures,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’00), Vol. 5, pp. v-705-708, Geneva, Switzerland, May 28-31, 2000. [39] Y. X. You, J. X. Wang, F. C. Lai, and Y. Z. Ye, “Design and Implementation of High-Speed Reed-Solomon Decoder,” Proceedings of the 1st IEEE International Conference on Circuits and Systems for Communications , pp. 146-149, 26-28 June 2002. [40] Agilent 83433A 10 Gb/s Lightwave Receiver Product Overview. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17531 | - |
dc.description.abstract | 在高速數據串列傳輸的應用上,為了能夠偵測並且加以修正因為傳輸通道非理想特性而造成的錯誤,在傳輸時常常會將原來欲傳輸的訊號,編碼成帶有特殊樣式的錯誤更正碼,對抗來自於通道中的隨機錯誤或是叢集錯誤所帶來的影響。爾後透過解碼,偵測其接收的訊號中錯誤位置的所在,並且加以修正,以得到原來乾淨的訊息。里德所羅門碼,便是其中一種能夠偵測,並且加以更正的錯誤更正碼。
在晶片實作中,為了同時兼顧高速傳輸的需求,以及符合晶片中心對於下線面積的限制,我們實現了規格為(n,k,t)=(15,9,3)的里德所羅門編解碼器,在傳輸的15個符號單位中,其中有9個符號是原始訊息,且可更正至多3個符號的傳輸錯誤。在實作上使用TSMC 0.35μm 2P4M CMOS製程,電源供應為3.3 V,電路的速率可以達到125 MHz,晶片總面積為1.462 X 1.462 mm2,總功率消耗為197.3 mW。晶片量測採用國家晶片系統設計中心的混合訊號自動測試機台,驗證本晶片功能的正確性,並且將此里德所羅門編解碼器用於高速串列傳輸系統。 在高速串列傳輸之里德所羅門編解碼器系統實作中,使用Xilinx公司的ML507 Evaluation Platform做為開發平台,並且制定同步高速串列傳輸系統通信協議。定義一個框架為120位元,其中有4個同步位元,84個資料位元,以及32個錯誤更正碼冗餘位元。實現此通信協議使用以下模組,包含擾碼器和解擾碼器、里德所羅門編碼器和解碼器、交錯器和解交錯器、跨時脈域雙埠記憶體、同步位元對齊模組、串列器和解串列器。系統測試則使用迴路測試以及光纖通訊系統測試來驗證系統的正確性,成功實作一個可調整線速率範圍在3Gbps到5Gbps的高速串列傳輸之里德所羅門編解碼器系統。 | zh_TW |
dc.description.abstract | In the application of the high-speed serial transmission, due to non-ideal transmission channel we usually encode original messages into the particular patterns, or so-called error-correcting code such that the errors can be detected and corrected. The channel noise may result from random noise and burst noise. Through decoding, these transmission errors can be detected and corrected. Reed Solomon code is one of the error-correcting code which is capable of detecting and correcting errors.
For chip implementation, considering the high-speed application and the limitations of chip area, we eventually implement a Reed-Solomon Codec whose specification is (n,k,t)=(15,9,3). In the other words, there are nine symbols of original messages over fifteen symbols during transmission and up to three error symbols can be tolerated. For the implementation, we use TSMC 0.35μm 2P4M CMOS process, and the voltage supply is 3.3 Volts. As the result, operating frequency of the circuit can be as high as 125 MHz, while the corresponding area is 1.462 X 1.462 mm2 and the total power consumption is 197.3 mW. In the chip measurements, we use the National Chip Implementation Center mixed-signal automatic test machine to verify the functionality of the chip. We could apply this Reed-Solomon Codec for the high-speed serial transmission systems. In the implementation of Reed-Solomon Codec for high-speed serial transmission using the Xilinx ML507 Evaluation Platform as a development platform, we develop high-speed synchronous serial transmission system protocol that defines a frame of 120 bits, of which there are 4 synchronization bits, 84 data bits, and 32 redundant error-correcting bits. This protocol is implemented by using various modules, including scrambler and descrambler, Reed-Solomon Codec, interleaver and de-Interleaver, clock-domain-crossing dual-port RAM, synchronous bit alignment module, serializer and deserializer. In the system tests, we use the loop test and the fiber optic communications system test to verify the correctness of the system. We successfully implement a Reed-Solomon Codec for high-speed serial transmission system whose line rate range is 3Gbps to 5Gbps. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:18:55Z (GMT). No. of bitstreams: 1 ntu-102-R99941111-1.pdf: 6350148 bytes, checksum: b04f8f306c09b131b1a9477eade00b09 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 iii ABSTRACT v 目錄 vii 圖目錄 xi 表目錄 xvii Chapter 1 緒論 1 1.1 前言 1 1.2 數位通訊系統基本架構 2 1.3 高速串列傳輸之概念與應用 4 1.4 論文組織 7 Chapter 2 里德所羅門碼 9 2.1 通道編碼之概念 9 2.2 加羅瓦場數學基礎 10 2.3 里德所羅門碼之加羅瓦場建立 12 2.4 里德所羅門碼應用及參數介紹 15 Chapter 3 實現里德所羅門編解碼器 17 3.1 里德所羅門碼之編碼演算法和電路架構 17 3.2 里德所羅門碼之解碼演算法和電路架構 19 3.2.1 計算錯誤徵狀值模組 22 3.2.2 Modified Euclidean演算法求解關鍵方程式模組 24 3.2.3 計算錯誤位置之演算法模組 29 3.2.4 計算錯誤值之演算法模組 30 3.3 里德所羅門編解碼器晶片實作 33 3.3.1 晶片設計流程 33 3.3.2 晶片電路模擬 35 3.3.3 晶片驗證結果 39 3.3.4 晶片佈局平面圖 41 3.3.5 晶片量測結果 42 3.4 本章總結 51 Chapter 4 高速串列傳輸之收發器技術 53 4.1 基本差分信號和通信同步概念 53 4.1.1 基本差分信號概念 53 4.1.2 系统同步、源同步和自同步 54 4.1.3 同步串列傳輸和非同步串列傳輸 58 4.2 高速串列傳輸SERDES之功能模組 59 4.3 線路編碼機制的工作原理 61 4.3.1 8b/10b編碼/解碼機制 61 4.3.2 擾碼機制 65 4.3.3 64/66b編碼/解碼機制 66 Chapter 5 實現高速串列傳輸之里德所羅門編解碼器 71 5.1 高速串列傳輸之里德所羅門編解碼器系統設計 71 5.1.1 同步高速串列傳輸系統通信協議 72 5.1.2 同步高速串列傳輸系統架構設計 74 5.2 實現高速串列傳輸之里德所羅門編解碼器 77 5.2.1 擾碼器和解擾碼器 77 5.2.2 交錯器和解交錯器 78 5.2.3 跨時脈域雙埠記憶體 79 5.2.4 同步位元對齊模組 80 5.2.5 串列器和解串列器 81 5.2.6 高速串列傳輸系統之FPGA實作與使用資源分析 86 5.3 高速串列傳輸之里德所羅門編解碼器系統驗證與量測 89 5.3.1 系統驗證方式和量測系統介紹 89 5.3.2 驗證與量測結果 93 5.4 本章總結 103 Chapter 6 結論 105 6.1 論文貢獻 105 6.2 未來展望 107 參考文獻 111 | |
dc.language.iso | zh-TW | |
dc.title | 適用於高速串列傳輸之里德所羅門編解碼器設計及硬體實現 | zh_TW |
dc.title | Design and Hardware Implementation of Reed-Solomon Codec for High-Speed Serial Transmission | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 吳靜雄 | |
dc.contributor.oralexamcommittee | 李三良,陳伯奇 | |
dc.subject.keyword | 錯誤更正碼,通道編碼,里德所羅門編解碼器,高速串列傳輸系統,同步串列通訊協議,現場可程式化邏輯陣列,數據通訊, | zh_TW |
dc.subject.keyword | Error-correcting code,Channel coding,High-speed serial transmission system,Reed-Solomon codec,Synchronous serial communication protocol,Field programmable gate arrays (FPGA),Data communications, | en |
dc.relation.page | 114 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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