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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Yen-Yu Chao | en |
dc.contributor.author | 趙晏榆 | zh_TW |
dc.date.accessioned | 2021-06-08T00:05:03Z | - |
dc.date.copyright | 2021-02-22 | |
dc.date.issued | 2021 | |
dc.date.submitted | 2021-02-05 | |
dc.identifier.citation | Y. C. Huang and S. I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Feb. 2013. M. Kim, S. Choi, and J. Choi, “A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2015, pp. C142–C143. Y. Lee, H. Yoon, M. Kim, and J. Choi, “A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 238-239, June 2016. G. Y. Wei, J. T. Stonick, D. Weinlader, J. Sonntag and S. Searles, “A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25um CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2003. A. Elshazly, B. Young, P. K Hanumolu, “Clock multiplication techniques using digital multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416–1428, Jun. 2013. H. Kim, Y. Kim, T. Kim, and H. Ko, “A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2016. Y. K. Chiu and S. I. Liu, “A PVT-tolerant MDLL using a frequency calibrator and a voltage monitor,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2698-2702, Nov. 2019. S. Ye, L. Jansson and I. Galton, “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002. R. Farjad-Rad et al., “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804-1812, Dec. 2002. B. M. Helal, M. Z. Straayer, G. Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855–863, Apr. 2008. Q. Du, J. Zhuang and T. Kwasniewski, “A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1205–1209, Nov. 2006. J. Kim and S. Han, “A fast-locking all-digital multiplying DLL for fractional-ratio dynamic frequency scaling,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 3, pp. 276-280, March 2018. Y. C. Yang, S. A. Yu, T. Wang and S. S. Lu, “A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 11, pp. 754-756, Nov. 2005. B. Razavi, RF Microelectronics, 2nd ed. Prentice Hall, pp. 635, 2011. S. Levantino et al., “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2678-2691, Nov. 2015. A. Santiccioli et al., “A 1.6-to-3.0-GHz fractional-N MDLL with a digital-to-time converter range-reduction technique achieving 397fs jitter at 2.5-mW power,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, 2019. L. Grimaldi et al., “A 30GHz digital sub-sampling fractional-N PLL with 198fsrms jitter in 65nm LP CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2019. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17287 | - |
dc.description.abstract | 本論文實現一個快速鎖定以及抗諧波之倍頻延遲鎖定迴路。透過使用一個相位偵測器附帶選擇邏輯電路,此倍頻延遲鎖定迴路將可以抗諧波鎖定。透過使用快速鎖定電路後,當除頻器之除數由60切換至65,此倍頻延遲鎖定迴路之鎖定時間為295.77ns,約為8個參考時脈週期。這個倍頻延遲鎖定迴路使用台積電40奈米CMOS製程製作且其面積約為0.0088mm2。在供應電壓為1V下,其功率消耗為3.4mW,量測之參考突波為-45.1dBc,在1MHz偏移頻率下,量測之相位雜訊為-106.59dBc/Hz,且在輸出頻率1.5GHz時,量測之方均根抖動量為2.995ps。 | zh_TW |
dc.description.abstract | In this thesis, a fast-locking and anti-harmonic multiplying delay-locked loop (MDLL) is presented. By using the proposed phase detector with a select logic, the MDLL will be anti-harmonic. By using the fast-locking circuit, the locking time of the MDLL is 295.77ns around 8 reference clock cycles, while the division ratio is switched from 60 to 65. This MDLL is fabricated in a 40 nm CMOS process and its core area is 0.0088mm2. The power consumption of the MDLL is 3.4mW for a supply voltage of 1V. The measured reference spur is -45.1dBc. The measured phase noise is -106.59dBc/Hz at the offset frequency of 1MHz and the integrated rms jitter is 2.995ps at 1.5GHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:05:03Z (GMT). No. of bitstreams: 1 U0001-0402202123461700.pdf: 2629803 bytes, checksum: a512f389f3756117126076e768185415 (MD5) Previous issue date: 2021 | en |
dc.description.tableofcontents | 1.1 Motivation 1 1.2 Overview 2 2. Prior Research 4 2.1 Review of anti-harmonic MDLL 4 2.2 Review of fast-locking MDLL 5 3. A Fast-Locking Multiplying Delay-Locked Loop 6 3.1 The Proposed MDLL with Fast-Locking Circuit 6 3.2 Circuit Description 7 3.2.1 Select Logic and Modified PD 7 3.2.2 Frequency Detector 11 3.2.3 DAC and Controller 13 3.2.4 Voltage-Controlled Oscillator and Charge Pump 15 3.2.5 Programmable Divider 16 3.3 MDLL Noise Analysis 17 3.4 Simulation Results 19 3.5 Measurement Setup and Experiment Results 23 3.6 Performance Summary 29 4. Conclusion and Future Work 31 4.1 Conclusion 31 4.2 Future Work 32 Bibliography 33 Appendix 35 A.1 Abstract 35 A.2 Fractional-N MDLL 36 A.3 Circuit Description 37 A.3.1 Delta-Sigma Modulator 37 A.3.2 Digital-to-Time Converter and Least Mean Square Algorithm 39 A.3.3 Reduction of the Tuning Range of DTC 42 A.4 Simulation Results 43 A.5 Conclusion 44 | |
dc.language.iso | en | |
dc.title | 一個快速鎖定之倍頻延遲鎖定迴路 | zh_TW |
dc.title | A Fast-Locking Multiplying Delay-Locked Loop | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee) | |
dc.subject.keyword | 快速鎖定,抗諧波,倍頻延遲鎖定迴路,頻率偵測器, | zh_TW |
dc.subject.keyword | fast-locking,anti-harmonic,multiplying delay-locked loop,frequency detector, | en |
dc.relation.page | 44 | |
dc.identifier.doi | 10.6342/NTU202100549 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2021-02-08 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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