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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Ying-Han Lee | en |
dc.contributor.author | 李盈翰 | zh_TW |
dc.date.accessioned | 2021-06-07T23:53:22Z | - |
dc.date.copyright | 2013-11-05 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-10-24 | |
dc.identifier.citation | [1] Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, and Paul D. Franzon,'3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver' IEEE Journal Of Solid-State Circuits, VOL. 41, NO. 1, January 2006, Page(s): 287 - 296
[2] Thaddeus J. Gabara and Wilhelm C. Fischer, 'Capacitive coupling and quantized feedback applied to conventional CMOS technology' IEEE Journal Of Solid-State Circuits, VOL. 32, NO. 3, March 1997 , Page(s): 419 - 427 [3] Jongsun Kim, Ingrid Verbauwhede and Mau-Chung Frank Chang, 'A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus' IEEE Journal Of Solid-State Circuits, VOL. 40, NO. 6, June 2005 , Page(s): 1331 - 1340 [4] Stephen Mick, John Wilson and Paul Franzon,'4 Gbps high-density AC coupled interconnection' Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002, Page(s): 133 – 140 [5] Stefan A.Kuhn, Michael B.Kleiner, Roland Thewes and Werner Weber,'Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling' Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on Volume: 1,Page(s): 37 – 40 [6] Hui Zhang, Varghese George and Jan M.Rabaey,'Low-swing on-chip signaling techniques: effectiveness and robustness'IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 8, NO. 3, JUNE 2000 , Page(s): 264 - 272 [7] Robert J. Drost, Robert David Hopkins, Ron Ho and Ivan E.Sutherland,'Proximity communication'IEEE Journal Of Solid-State Circuits, VOL. 39, NO. 9, September 2004 , Page(s): 1529 - 1535 [8] John Wilson, Stephen Mick, Jian Xu, Lei Luo, Salvatore Bonafede, Alan Huffman, Richard LaBennett and Paul D. Franzon,'Fully Integrated AC Coupled Interconnect Using Buried Bumps'IEEE Transactions On Advanced Packaging, VOL. 30, NO. 2, May 2007 , Page(s): 191 - 199 [9] David Salzman, Thomas Knight, Paul Franzon,'Application of Capacitive Coupling to Switch Fabrics'Multi-Chip Module Conference, 1995, Page(s): 195 – 199 [10] Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda and Takayasu Sakurai,'1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme'IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers, Page(s): 186 - 487 vol.1 [11] Leonard A.Hayden and Vijai K.Tripathi,'Pulse signaling using Capacitively-Coupled CMOS'IEEE 3rd Topical Meeting on Electrical Performance of Electronic packaging, 1994, Page(s): 7 – 9 [12] Muhammad Usama and Tad Kwasniewski,'New CML latch structure for high speed prescaler design'Canadian Conference on Electrical and Computer Engineering, 2004., Page(s): 1915 - 1918 Vol.4 [13] Manabu Ishibe, Shoji Otaka, Junichi Takeda, Shigeru Tanaka, Yoshiaki Toyoshima, Satoru Takatsuka and Shoichi Shimizu,'High-speed CMOS I/O buffer circuits',IEEE Journal Of Solid-State Circuits,VOL 27,NO 4,April 1992 , Page(s): 671 - 673 [14] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001 [15] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2001 [16] Payam Heydari and Ravi Mohavavelu,'Design of ultra high-speed CMOS CML buffers and latches'Proceedings of the 2003 International Symposium on Circuits and Systems, 2003., Page(s): II-208 - II-211 vol.2 [17] Masum Hossain and Anthony Chan Carusone,'5–10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS'IEEE Journal Of Solid-State Circuits, VOL. 45, NO. 3, March 2010, Page(s): 524 - 537 [18] Kwisung Yool, Dongmyung Lee, Gunhee Han and Sung Min Park,'A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation'IEEE International Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers., Page(s): 56 – 57 [19] Hamid Partovi, Karthik Gopalakrishnan, Luca Ravezzi, Russell Homer, Otto Schumacher, Reinhold Unterricker, Werner Kederer,'Single-ended transceiver design techniques for 5.33Gb/s graphics applications'IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2009., Page(s): 136 - 137 [20] R. Palmer, J. Poulton, W. J. Dally, J. Eyles, A. M. Fuller, T. Greer, M. Horowitz, M. Kellam, F. Quan, F. Zarkeshvari,'A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip'IEEE International Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers., Page(s): 440-614 [21] Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fan-Ta Chen, Ching-Te Chiu and Shawn S. H. Hsu,'A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18um CMOS Technology'IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 17, NO. 5, May 2009 , Page(s): 688 - 696 [22] Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin and Charlie Chung-Ping Chen,'A 12 Gb/s chip-to-chip AC coupled transceiver'IEEE International Symposium on Circuits and Systems (ISCAS), 2011, Page(s): 1692 – 1695 [23] Ka Nang Leung and Philip K. T. Mok,'A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation'IEEE Journal Of Solid-State Circuits, VOL. 38, NO. 10, October 2003 , Page(s): 1691 - 1702 [24] Sai Kit Lau, Philip K. T. Mok and Ka Nang Leung,'A low-dropout regulator for SoC with Q-reduction'IEEE Journal Of Solid-State Circuits, VOL. 42, NO. 3, March 2007 , Page(s): 658 - 664 [25] Robert J. Milliken, Jose Silva-Martínez and Edgar Sánchez-Sinencio,'Full on-chip CMOS low-dropout voltage regulator'IEEE Transactions on Circuits and Systems I: Regular Papers,2007, Page(s): 1879 – 1890 [26] Tsz Yin Man, Ka Nang Leung, Chi Yat Leung,Philip K. T. Mok and Mansun Chan,'Development of single-transistor-control LDO based on flipped voltage follower for SoC'IEEE Transactions On Circuits And Systems—I: Regular Papers, VOL. 55, NO. 5, June 2008 , Page(s): 1392 - 1401 [27] Wonseok Oh and Bertan Bakkaloglu,'A CMOS low-dropout regulaor with current-mode feedback buffer amplifier'IEEE Transactions On Circuits And Systems—II: Express Briefs, VOL. 54, NO. 10, October 2007 , Page(s): 922 - 926 [28] Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan and Shekhar Borkar,'Area-efficient linear regulator with ultra-fast load regulation'IEEE Journal Of Solid-State Circuits, VOL. 40, NO. 4, April 2005, Page(s): 933 – 940 [29] Mohammad Al-Shyoukh, Hoi Lee and Raul Perez,'A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation'IEEE Journal Of Solid-State Circuits, VOL. 42, NO. 8, August 2007, Page(s): 1732 – 1742 [30] Yat-Hei Lam, Wing-Hung Ki and Chi-Ying Tsui,'Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback'Asia and South Pacific Conference on Design Automation, 2006 [31] Gabriel A. Rincon-Mora and Phillip E. Allen,'A low-voltage, low quiescent current, low drop-out regulator'IEEE Journal Of Solid-State Circuits, VOL. 33, NO. 1, January1998, Page(s): 36 – 44 [32] Gabriel A. Rincon-Mora,'Active capacitor multiplier in Miller compensated circuits'IEEE Journal Of Solid-State Circuits, VOL. 35, NO. 1, January 2000, Page(s): 26 – 32 [33] Sau Siong Chong and Pak Kwong Chan,'A 0.9uA Quiescent Current Output Capacitor-less LDO Regulator With Adaptive Power Transistors in 65-nm CMOS'IEEE Transactions On Circuits And Systems—I: Regular Papers, VOL. 60, NO. 4, April 2013, Page(s): 1072 – 1081 [34] Wu,C.-H., Chang-Chien,'Design of the output-capacitor-less low-dropout regulator for nano-second transient response', Power Electronics, IET, Sep. 2012, Page(s): 1551 – 1559 [35] Gabriel Alfonso Rincon-Mora,”Analog IC Design with LOW-DROPOUT REGULATORS” McGraw-Hill, 2004 [36] Bang S. Lee, “Understanding the terms and definitions of LDO voltage Regulators” , Texas Instruments | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17019 | - |
dc.description.abstract | 因為製程的演進,晶片內部的時脈也越來越快,但是晶片與晶片間的傳輸速度卻相對的進步緩慢。因此,設計出一個高速的傳送接收器變成一個重要的課題。
本論文提出了一個高速且低功率耗損應用於晶片間傳輸的電容耦合式接收器,在第一顆晶片裡包含了一個耦合電容(75fF)、一個低擺幅脈衝接收器,以及一個限制放大器。在此種電路架構裡面,信號是以脈衝波形在傳輸線中做傳送,透過電容值的選取,可以有效的控制脈衝波的振幅和長度,以降低ISI,此晶片可運作在12Gb/s速度。脈衝波形經由傳輸線傳遞後再由低擺幅脈衝接收器作訊號回復至NRZ訊號,同時此脈衝接收器也具有低頻補償的功用。在第二顆晶片裡改進了第一顆,使用了線性補償,包含了一個限制放大器、一個低擺幅脈衝接收器、一個線性放大器和一個加法器已達到20Gb/s的操作速度。在第三顆晶片,是做了一個低靜態電流、無輸出電容的低降壓穩壓器,目的是為了能夠提供穩定的電壓源給傳輸晶片系統使用。 第一顆晶片是用TSMC 90nm RF CMOS 製成再做驗證並製作出來,晶片面積為0.135mmX0.056mm。第二顆晶片是用TSMC 90nm UTM CMOS製成再做驗證並製作出來,晶片面積為0.071mmX0.214mm。由模擬結果可以看出第二顆晶片改進了第一顆晶片。 最後,我們也設計了一顆低降壓穩壓器在TSMC 0.35um CMOS製成,做驗證並製作出來,晶片面積為0.477mmx0.742mm。低降壓穩壓器最大負載電流170mA,輸入電壓源(2~6V)皆能穩壓在設定的電壓值,模擬驗證結果在附錄中。 | zh_TW |
dc.description.abstract | Today, the scaling of MOS transistor dimensions is a key factor in the improvement of performance of CMOS technology. High speed links with small AC coupling capacitances are increasing in importance. As a result, the receiver receives a stream of positive and negative pulses corresponding to the rising and falling edges of transmitted data. Receivers which are capable of recovering NRZ signals from these narrow pulses are referred to in this work as AC coupled receivers, and are not to be confused with receivers for links with a relatively large DC blocking capacitor where the received waveforms still look like an NRZ signal with some baseline wander.
This thesis introduces a high-speed 12 Gb/s AC coupled receiver architecture for high density interconnects and a modified design for the 1st design which can operate at the 20Gb/s. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from a 75fF capacitor coupled channel. Due to the small coupling capacitances, the transmitted NRZ data at high frequency transitions can be detected at the receiver. The main challenge of the receiver front end is to recover NRZ data from the low swing pulses. In conclusion, 2 chips are designed and fabricated in TSMC 90nm CMOS technology. The 1st proposed chip is using a novel hysteresis circuit path without any compensation technique. The 2nd proposed chip improve the 1st chip integrated with time domain compensation. In addition, we also designed a Low dropout, low quiescent current, output capacitor-less regulator showed in appendix. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T23:53:22Z (GMT). No. of bitstreams: 1 ntu-102-R00943038-1.pdf: 4180189 bytes, checksum: 9a1ca70666cb64490fbb98081039b8b2 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 II 中文摘要 III ABSTRACT IV Contents VI List OF Figures IX List OF Tables XIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Background of AC Coupled Interconnects 4 2.1 Introduction 4 2.2 Circuit structures of AC Coupled Interconnect 9 2.3 Pulse signaling on ACCI 11 2.4 Frequency response of ACCI 14 2.5 Comparison of ACCI and other I/Os 17 2.6 Summary 19 Chapter 3 1st work ACCI Receiver 20 3.1 Introduction 20 3.2 Hysteresis analysis 22 3.3 Limiting Amplifier 27 3.4 Layout 33 Chapter 4 Measurement Results of ACCI 34 4.1 Measurement setup 34 4.2 Equipments 35 4.3 Layout, results and specification 36 Chapter 5 Modified AC Coupled Design with linear compensation 42 5.1 Introduction 42 5.2 Whole Architecture 42 5.3 Pre amplifier 42 5.4 Hysteretic Analysis 45 5.5 Linear Amplifier 47 5.6 Adder 50 5.7 Layout 52 5.8 Post Layout Simulation 54 Chapter 6 Conclusion and future work 55 Chapter 7 Appendix – LDO Regulator 57 7.1 Introduction Regulators in Power Management 57 7.2 Linear Versus Switching Regulator 59 7.3 Integration 60 7.4 Operational lifetime 61 7.5 Dropout 62 7.6 Block Level 63 7.7 Load Regulation 64 7.8 Line Regulation 65 7.9 Power Supply Rejection 65 7.10 Quiescent Current 66 7.11 Efficiency 66 7.12 Accuracy 67 7.13 Proposed No output Capacitor LDO 68 7.14 Simulation 71 Chapter 8 Measurement Results of LDO 75 8.1 Environment and results 75 8.2 Layout and specification 78 REFERENCE 81 | |
dc.language.iso | en | |
dc.title | 一個20Gb/s利用電容耦合傳輸資料之無電感介面電路 | zh_TW |
dc.title | An Inductor-less 20 Gb/s AC Coupled Chip-to-Chip Interconnect | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),陳少傑(Sao-Jie Chen),盧奕璋(Yi-Chang Lu) | |
dc.subject.keyword | 電容耦合接收器,晶片與晶片間傳輸,低擺幅脈衝接收器,互補式傳輸線,低降壓穩壓器, | zh_TW |
dc.subject.keyword | AC coupled interconnect receiver,low swing pulse receiver,high speed, | en |
dc.relation.page | 85 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-10-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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