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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 曹恒偉 | |
dc.contributor.author | Wen-Chen Fang | en |
dc.contributor.author | 方玟蓁 | zh_TW |
dc.date.accessioned | 2021-06-07T23:47:58Z | - |
dc.date.copyright | 2014-03-25 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-03-21 | |
dc.identifier.citation | [1] IEEE Std 802.3ba-2010.
[2] Enablence, 'PDCS12T 40 Gb/s InGaAs PHOTODIODE' [3] B. Razavi, 'Principle of Data Conversion System Design,' in IEEE PRESS, 1995. [4] Kuo, Chien-Hung, 'The Design and Implementation of Low Voltage CMOS Delta Sigma Modulators,' Graduate Institute of Electrical Engineering National Taiwan University Doctoral Dissertation, June 2003. [5] 'Understanding Data Converters Application Report,' in TEXAS INSTRUMENTS, 1995. [6] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, 'CMOS DATA CONVERTERS FOR COMMUNICATION,' Kluwer Academic Publishers, 2000. [7] B. M. Gordon, 'Linear electronic analog/digital conversion architectures, their origins, parameters, limitations, and applications,' in IEEE Trans. Circuits Cyst., vol. CAS-25, pp. 391-418, July 1978. [8] J. Sit and R. Sarpeshkar, 'A micropower logarithmic A/D with offset and temperature compensation,' in IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 308–319, Feb. 2004. [9] J. Lee, J. Kang, et al., 'A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC,' in IEEE J. Solid-State Circuits, vol.44, no.10, pp.2755-2765, Oct. 2009. [10] Dessouky, M.; Kaiser, A., 'Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,' in Electronics Letters , vol.35, no.1, pp.8,10, 7 Jan 1999. [11] B. Razavi and B. Wooley, 'Design techniques for high-speed, high- resolution comparators,' in IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992. [12] M. Van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink and B. Nauta, 'A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,' in ISSCC Dig. Tech. Papers, Feb. 2008. [13] Rincon-Mora, G.; Allen, P.E., 'A low-voltage, low quiescent current, low drop-out regulator,' Solid-State Circuits, in IEEE Journal of , vol.33, no.1, pp.36,44, Jan 1998. [14] B. Razavi, 'Design of Analog CMOS Integrated,' McGraw Hill, 2001. [15] Finisar, '802.3ba 40GE/100GE SMF SRS Test Proposal,' in IEEE 802.3ba Task Force 13 -16 July 2009. [16] Ginsburg, B.P., and Chandrakasan, A.P. , 'An energy-efficient charge recycling approach for a SAR converter with capacitive DAC ,' in IEEE Int. Symp. on Circuits and Systems, May 2005, pp.184–187. [17] Chang, Y., Wang, C., and Wang, C., ' A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,' in IEEE Asian Solid-State Circuits Conf., 2007, Jeju, Korea, November 2007, pp. 228–231. [18] Liu, C., Chang, S., Huang, G., and Lin, Y., 'A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 mm CMOS process,' Symp. on VLSI Circuits Digest of Technical Papers, June 2009, pp. 236–237. [19] Hariprasath, V.; Guerber, J.; Lee, S.-H.; Moon, U.-K., 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' in Electronics Letters , vol.46, no.9, pp.620,621, April 29 2010. [20] Zhu, Y., Chan, C.H., Chio, U.F., Sin, S.W., U, S.P., Martins, R.P., and Maloberti, F.: 'A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,' IEEE J. Solid-State Circuits, 2010, 45, (6), pp. 1111–1121 [21] Kuo, C.H.; Hsieh, C.E., 'Floating capacitor switching SAR ADC,' in Electronics Letters , vol.47, no.13, pp.742,743, June 23 2011. [22] Jongwoo Lee; Hyo-Gyuem Rhew; Kipke, D.R.; Flynn, M.P., 'A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC,' Solid-State Circuits, in IEEE Journal of, vol.45, no.9, pp.1935,1945, Sept. 2010. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16852 | - |
dc.description.abstract | 對數型數位類比轉換器可偵測大範圍變動之訊號,亦可簡化後方的數位運算。本論文提出一低功率消耗的電路實現,相較於傳統線性型逐次逼近暫存器式類比數位轉換器[16],可節省99.6%的切換能量;此對數型類比數位轉換器僅須一個參考電壓、且具有雙基底轉換功能之對數型類比數位轉換器,我們並基於此架構設計出應用於偵測光或電訊號平均強度之接收訊號強度指標電路。
晶片實作分成兩個版本:8位元1.25MS/s雙基底對數型類比數位轉換器、及8位元625KS/s光或電訊號平均強度偵測電路。兩者的類比電路供給電壓是1.65V和3.3V,數位電路是0.9V,皆使用0.18um互補式金氧半場效電晶體製程,晶片面積均是 。 於第四章介紹之第一個版本的動態範圍48dB,其直流DNL峰值是0.55 -LSB、INL峰值是0.96-LSB,功率消耗240uW,FOM (pJ/conv. step)約為0.5。 於第五章介紹之第二個版本的動態範圍96dB,其直流DNL峰值是0.75 -LSB、INL峰值是1- LSB,功率消耗320uW,FOM (pJ/conv. step)約為2.1。 | zh_TW |
dc.description.abstract | Logarithmic analog to digital converter can detect signal changes with wide dynamic range, and also benefits digital computation.
A low power logarithmic analog to digital converter that needs only one signal reference voltage and has double bases is presented in this thesis. Based on this architecture, we then design the circuit as a receive signal strength indicator (RSSI) for average optical or electronic signal strength detection. Two versions chips are implemented:An 8-bit 1.25MS/s double -base logarithmic analog to digital converter, and an 8-bit 625KS/s circuit for average optical/electronic signal strength detection. Both of them have dc supplies of 1.65V or 3.3V for analog circuit, and 0.9V for digital circuit. The chips are fabricated in 0.18um CMOS process in the same area of . The first version in chapter 4 has 48dB dynamic range, achieving 0.55-LSB peak DNL and 0.96-LSB peak INL. It consumes 240uW and the FOM (pJ/conv. step) is 0.5. The second version in chapter 5 has 96dB dynamic range, achieving 0.75-LSB peak DNL and 1-LSB peak INL. It consumes 320uW and the FOM (pJ/conv. step) is 2.1. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T23:47:58Z (GMT). No. of bitstreams: 1 ntu-103-R00943035-1.pdf: 3994310 bytes, checksum: 697cb39891c57ffa6873eb2726242bb7 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 誌 謝 I
摘 要 III Abstract V 目 錄 VII 圖目錄 XI 表目錄 XV 第一章 概論 1 1.1 研究背景 1 1.2 研究動機及目的 1 1.3 論文組織 3 第二章 類比數位轉換器技術原理 5 2.1 類比數位轉換器簡介 5 2.1.1 量化誤差(Quantization error) 6 2.2 效能衡量標準 8 2.2.1 靜態特性參數 8 2.2.2 動態特性參數 11 第三章 類比數位轉換器架構分類簡介 15 3.1 奈奎斯速率線性型類比數位轉換器 15 3.1.1 快閃式(Flash)[3] 15 3.1.2 雙斜率式(Dual Slope)[7] 20 3.1.3 管線式(Pipelined)[3] 21 3.1.4 逐次逼近暫存器式(Successive-Approximation Register, SAR)[3] 21 3.1.5 時脈間插式(Time-interleaved)[3] 22 3.2 超取樣線性型類比數位轉換器[4] 23 3.2.1 三角積分調變式(Σ-Δ modulators) 23 3.3 奈奎斯速率對數型類比數位轉換器 24 3.3.1 自然對數型雙斜率式(Natural Logarithmic Dual Slope)[8] 24 3.3.2 對數型管線式(Logarithmic Pipelined)[9] 25 3.4 本章結論 27 第四章 雙基底對數型類比數位轉換器 29 4.1 取樣保持電路(Sample and Hold,S/H)[3] 29 4.1.1 靴帶式開關(Bootstrapped Switch)[10] 35 4.2 比較器(Comparator)[3] 39 4.2.1 自動歸零技術(Auto Zero)[11] 42 4.2.2 節能動態二級比較器(Energy-efficient Dynamic two Stage Comparator)[12] 44 4.2.3 具自動零偏移消除節能動態多級比較器(Auto-zero Offset Cancellation Energy-efficient Dynamic Multi-stage Comparator) 46 4.3.1 能隙(Bandgap)電路模擬 50 4.3.2 低壓降線性穩壓器(Low Dropout Linear Regulator﹐LDO)電路模擬 52 4.4 雙基底對數型類比數位轉換器電路原理及模擬 54 4.4.1 雙基底對數型類比數位轉換器MSB_stage電路 55 4.4.2 雙基底對數型類比數位轉換器LSB_stage電路 57 4.4.3 雙基底對數型類比數位轉換器佈局後模擬 62 4.4.4 雙基底對數型類比數位轉換器晶片量測 63 第五章 光與電訊號平均強度偵測電路 71 5.1 訊號強度偵測(Received Signal Strength Indication, RSSI)[15] 71 5.2 光與電訊號平均強度偵測電路 72 第六章 結論與未來展望 83 6.1 比較其他文獻 83 6.2 未來改進方向 85 參考文獻 87 | |
dc.language.iso | zh-TW | |
dc.title | 低功耗雙基底對數型類比數位轉換器 | zh_TW |
dc.title | A Low Power Double-base Logarithmic Analog to Digital Converter | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳伯奇,黃崇禧,陳建中,李泰成 | |
dc.subject.keyword | 互補式金氧半場效電晶體,接收訊號強度指標,對數型類比數位轉換器, | zh_TW |
dc.subject.keyword | CMOS,Receiving Signal Strength Indicator (RSSI),Logarithmic Analog to Digital Converter(Log. ADC), | en |
dc.relation.page | 89 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2014-03-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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