請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16798完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Rui Mao | en |
| dc.contributor.author | 毛睿 | zh_TW |
| dc.date.accessioned | 2021-06-07T23:46:18Z | - |
| dc.date.copyright | 2014-07-04 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-06-19 | |
| dc.identifier.citation | [1] W. R. Davis et al., “Demystifying 3D ICs: The Pros and Cons of Going Vertical”, IEEE Design Test on Computers, Vol 22, Issue 8,pp. 498-510, Nov 2005.
[2] J. A. Davis et al. “Interconnect Limits on Gigascale Integration(GSI) in the 21st Century”, Proc. IEEE, Vol 89, Issue 3, pp. 305-224, 2001. [3] P. Garrou, Christopher Bower and Pater Ramm, ”Handbook of 3D Integration”, Wiley-VCH, 2008. [4] Real World Technologies. '3D Integration: A Revolution in Design'. May 2, 2007. [5] S. Reda, G. Smith and L. Smith, “Maximizing the Functional Yield of Wafer-to- Wafer 3-D Integration”, IEEE Transactions on Very Large Scale Integration Systems, Vol 17, Issue 9, pp. 1357-1362, 2010. [6] E. Singh, “Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs”, IEEE VLSI Test Symposium, pp. 32-37, 2011. [7] J. Verbree, E.J. Marinissen, P. Roussel and D. Velenis, “On the Cost-Effectiveness of Matching Repositories of Pre-Tested Wafers for Wafer-to-Wafer 3D Chip Stacking”, IEEE European Test Symposium, pp. 36-41, May 2010. [8] M. Taouil, S. Hamdioui, J. Verbree and E.J. Marinissen, On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs, IEEE International Test Conference, pp. 1-10, 2010. [9] J. Munkres, 'Algorithms for the Assignment and Transportation Problems', Journal of the Society of Industrial and Applied Mathematics, 5(1):32-38, 1957. C. D. Jones, A. B. Smith, and E.F. Roberts, Book Title, Publisher, Location, Date. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16798 | - |
| dc.description.abstract | 隨著積體電路技術的不斷發展，電路尺寸更小，性能更高，成本也變得越來越高。使用矽穿孔(TSV)技術的三維記憶體是一種新興的技術，相比平面積體電路有更高的性能和更低的功耗。然而三維記憶體的堆疊產量仍然是一個問題。
在這篇論文中，我們提出了一個改進自匈牙利方法(The Hungarian Method of Assignment)的新演算法對三維記憶體(3D Memory)進行晶圓到晶圓堆疊。實驗結果表明我們的算法可以在一個合理的時間內，給出較高的堆疊良率。 | zh_TW |
| dc.description.abstract | As the process technology continues to evolve, IC become smaller and high performance, and the cost become higher. A 3D-IC uses Through Silicon Via (TSV) is an emerging technology, higher performance, and lower power consumption compared to planar ICs. However stacking yield is a problem of 3D-IC.
In this thesis, we propose a new algorithm using improved from the hungarian method of assignment on the three-dimensional memory for wafer to wafer stacking. Our results show that our algorithm can be a reasonable amount of time, given the higher stacking yield. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T23:46:18Z (GMT). No. of bitstreams: 1 ntu-103-R00943152-1.pdf: 919985 bytes, checksum: 36fca3d235803227306bf94982b93e4c (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES vii Chapter 1 Introduction 1 1.1 採用矽穿孔技術的三維積體電路 1 1.2 三維積體電路的堆疊技術 2 1.3 晶圓到晶圓堆疊的相關研究 3 1.4 論文目的 3 1.5 論文構成 3 Chapter 2 Preliminaries 5 2.1 指派問題 5 2.2 匈牙利方法 6 Chapter 3 The Proposed Method 12 3.1 三維記憶體堆疊問題 12 3.2 超平面覆蓋法 14 3.3 演算法的對稱性 19 3.4 相似度優先演算法 21 Chapter 4 Simulation Results 27 Chapter 5 Conclusions and Future Work 31 5.1 結論 31 5.2 未來工作 31 REFERENCE 33 | |
| dc.language.iso | zh-TW | |
| dc.title | 三維記憶體的晶圓到晶圓堆疊演算法 | zh_TW |
| dc.title | A 3D Memory Wafer To Wafer Stacking Algorithm | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),李進福(Jin-Fu Li) | |
| dc.subject.keyword | 三維記憶體,晶圓到晶圓,堆疊,演算法, | zh_TW |
| dc.subject.keyword | 3D Memory,Wafer To Wafer,Stacking,Algorithm, | en |
| dc.relation.page | 33 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-06-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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