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標題: | 差排應力記憶技術應用於矽基N型場效電晶體之研究 Demonstration of Dislocation Stress Memorization Technique (D-SMT) on Silicon nFET |
作者: | Kun-Han Liu 劉昆翰 |
指導教授: | 廖洺漢(Ming-Han Liao) |
關鍵字: | 閘極先製製程,差排應力記憶技術,鍺,固相磊晶成長,固相磊晶再成長,遮罩邊缺陷,差排, Gate-first,dislocation stress memorization technique (D-SMT),germanium,solid-phase epitaxial growth (SPEG),solid-phase epitaxial regrowth (SPER),mask edge defect,dislocation, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 本篇論文利用新穎的差排應力記憶技術配合閘極先製製程成功在矽基板上製作出了n型通道場效電晶體,同時量測其電性及分析施加差排應力記憶技術後對元件特性的影響;此外,利用穿透式電子顯微鏡觀察鍺在二維固相磊晶成長時差排缺陷是否形成的現象也一併被提出及討論。
本文第一部分製作出閘極長八微米且閘極寬為六十微米的差排應力記憶技術矽基n型通道場效電晶體並分析其電性。飽和電壓及轉移電導分別提升大約百分之十及百分之十五的結果可歸因於源極、汲極區內存在差排缺陷,此差排對元件通道施加了應變引致遷移率上升,即使高度張應力的氮化矽應力源被移除後此應力仍然存在於通道當中。高的開關電流比顯示元件品質並不會因為施加差排應力記憶技術而劣化。此外,載子遷移率的上升可由總電阻對閘極長度作圖的趨勢得到。未來可利用降低閘極長度、最佳化佈植參數、調整應力源、控制退火時間及溫度等條件來使得元件特性更加提升。 第二部分中,首先利用(001)方向的鍺基板去驗證其在<001>方向的固相磊晶成長速度;其次再經由預先非晶化佈植、退火等過程後利用穿透式電子顯微鏡觀察是否有差排缺陷產生。在非晶態鍺完全晶化後,我們並沒有在原先佈植的區域發現差排缺陷的產生。這可能是由於鍺在不同方向的固相磊晶成長速度差異較矽來的小,導致(001)及(110)成長界面的夾角在二維固相磊晶成長中受到影響。過去文獻指出,此兩界面的夾角為差排形成的重要參數。換句話說,當角度為銳角時,差排會較容易形成。據研究指出此夾角會受到固相磊晶成長中時環境的參雜物、外加應力、圖案引起之應力、或是方向性等原因影響。雖然對於鍺而言此結果不利於鍺在n型場效電晶體上應用差排應力記憶技術,對於不適合缺陷存在的p型場效電晶體而言卻或許是優點。 In this thesis, we demonstrated a novel dislocation stress memorization technique (D-SMT) silicon n-type field-effect transistor (nFET) by gate-first process which is considered to be low cost and simpler manufacturing. Observations of applying D-SMT on Si nFETs are electrically characterized and analyzed. We also investigated the dislocation formation of Ge during two-dimensional solid-phase epitaxial growth (SPEG) process and characterized by transmission electron microscopy (TEM). In first part, the D-SMT Si nFET with a gate lenth of SI{8}{um} and a gate width of SI{60}{um} was fabricated and electrically characterized. A saturation current and transconductance improvement of about 15\% and 10\% respectively were observed confirming that the strain-induced mobility enhancement was achieved by dislocations formation in the S/D recrystallized region. The strain retained even after nitride stressor removal in the process flow. High on/off ratio indicated that D-SMT process did not deteriorate the device quality. Furthermore, total resistance reduction with gate length scaling was observed with a higher mobility compared to control sample. With further gate pitch scaling and optimized parameters such as implantation profile, stress of capping film, annealing time and annealing temperature, the device performance would be further improved. In second part, (001)-oriented germanium was used to investigate the SPEG velocity along <100> direction and dislocation formation by pre amorphous implantation (PAI) and further annealing. After completely recrystallization of amorphous Ge, no dislocations was found to generate near the end-of-range (EOR). This might be caused by more isotropic SPEG orientation dependence of Ge compared to Si, which affected the angle $ heta$ between two growth fronts of (001) and (110) during two-dimensional SPEG. Historically, the $ heta$ has been considered as a significant parameter for dislocation (sometimes referred to mask edge defects) formation. That is, dislocations form much easier with an acute angle $ heta$, which has been reported to be affected by dopants, external applied stress, pattern-induced stress, and orientations during SPEG. Although this might be inconvenient for utilizing D-SMT in Ge nFETs, it might be advantageous for the use in Ge pFETs since dislocation defects would be undesirable in this case. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16652 |
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