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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Shih-Han Ku | en |
| dc.contributor.author | 古識涵 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:15:59Z | - |
| dc.date.copyright | 2012-03-19 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-02-14 | |
| dc.identifier.citation | [1] D. D. Caro, C. A. Romani, N. Petra, A. G. M. Strollo, and C. Parrella, “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1048–1060, May 2010.
[2] S.-Y. Lin and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, pp. 3111–3119, Nov. 2009. [3] D.-S. Shen and S.-I. Liu, “A low-jitter spread spectrum clock generator using FDMP,” IEEE Trans. on Circuits and Systems-II: Express Briefs, vol. 54, pp. 979–983, Nov. 2007. [4] H.-R. Lee, O. Kim, G. Ahn, and D.-K. Jeong, “A low-jitter 5000 ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18um CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2005, pp. 162–163. [5] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΣΔ modulator with level shifter,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2005, pp. 160–161. [6] K.-H. Cheng, C.-L. Hung, and C.-H. Chang, “A 0.77ps RMS jitter 6-GHz spread- spectrum clock generator using a compensated phase-rotating technique,” IEEE J. Solid-State Circuits, vol. 46, pp. 1198 - 1213, May 2011. [7] W. Cheng, Z. Tan, X. Gao, G. Chang, J. Wen, “High speed serial interface & some key technology research,” Electronic Commerce and Security, Aug. 2008, pp.562-566. [8] M. T. LoBue, “Surveying today’s most popular storage interfaces,” Computer, vol. 35, pp.48-55, Dec. 2002. [9] S. Bolger and S. Darwish, “Use spread-spectrum techniques to reduce EMI,” EDN, Boston, vol. 43, May 21, 1998. [10] F. Lin and D. Chen, “Reduction of power supply EMI emission by switching frequency modulation,” in The VPEC Tenth Annual Power Electronics Seminar, Virginia Power Electronics Center, Blacksburg, Virginia, Sep. 20-22, 1992. [11] D. S. Shen, “A spread spectrum clock generator based on a fractional-N frequency synthesizer,” MS Thesis, National Taiwan University, June 2007. [12] K. Hardin et al. “Spread spectrum clock generation for the reduction of radiated emissions,” in Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, Aug. 1994, pp.227-231. [13] K. Hardin, et al., “Spread spectrum clock generation and associated method,” US. Patent No. 5,488,627, Jan. 30, 1996. [14] H. Black, “Modulation Theory,” D. Van Nostrand Company, Inc., Princeton, NJ, 1953. [15] K. Mags, “Spread spectrum clocking to reduce EMI”, EE Times-India, April 2008. [16] Floyd M. Gardner, “Phaselock Techiques,” JOHN WILEY & SONS, INC., 2005 [17] R. B. Staszewski, P.T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS,” JOHN WILEY & SONS, INC., 2006 [18] V. Kratyuk, “Digital phase-locked loops for multi-GHz clock generation,” PhD Thesis, Oregon State University, Dec. 2006. [19] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, pp.1571-1580, Sept. 2004. [20] N. D. Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52, pp.505-509, Jan., 2005. [21] C. M. Hsu, 'Techniques for high-performance digital frequency synthesis and phase control,' PhD Thesis, Massachusetts Institute of Technology, Sep. 2008. [22] K. Hardin, J. T. Fessler, D. R. Bush. “Spread spectrum clock generation for the reduction of radiated emissions,” in Proceedings of the 1994 IEEE International Symposium on Electromagnetic Compatibility, Aug. 1994, pp.227-231. [23] M. Sugawara, T. Ishibashi, K. Ogasawara, M. Aoyama, M. Zwerg, S. Glowinski, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma, “1.5 Gbps, 5150 ppm spread spectrum serdes PHY with a 0.3 mW, 1.5 G/ps level detector for Serial ATA,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp.60-63. [24] M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, T. Ishibashi, S. Shimoyama, K. Yamaguchi, T. Yanagita, T. Noma, “3 Gbps, 5000 ppm spread spectrum serdes PHY with frequency tracking phase interpolators for Serial ATA,” in Symp. VLSI Circuits, June 2003, pp.107-110. [25] J. Y. Michel and C. Neron, “A frequency modulated PLL for EMI reduction in embedded application,” IEEE ASIC/SOC, vol.12, Sept. 1999, pp.362-365. [26] N. D. Dalt, E. Thaller, P. Gregorius, and L. Gazsi, “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp.1482-1490, July 2005. [27] Serial ATA Workgroup, “SATA: high speed serialized AT attachment,” Rev. 1, Aug. 2001. [28] P. Dudek, S. Szczepanski, and J.V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, pp. 240–247, Feb. 2000. [29] C. Lam and B. Razavi, “A 2.6GHz/5.2GHz frequency synthesizer in 0.4-um CMOS technology,” IEEE J, Solid-State Circuits, vol.35, pp. 788-794, May 2000. [30] S. Damphousse, K. Ouici, A. Rizki, and M. Mallinson, “All digital spread spectrum clock generator for EMI reduction,” IEEE J, Solid-State Circuits, vol.42, pp.145-150, Jan. 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16461 | - |
| dc.description.abstract | 這篇論文主要著重於展頻與解展頻方法的研究。主題分別為具有自我迴路頻寬校正的展頻時脈產生器以及應用於DisplayPort的解展頻時脈產生器。兩顆晶片皆使用0.18um CMOS的製程，並以全數位的方式實現。不同於耗面積的類比濾波器，以高密度的先進製程實現的數位濾波效果可以達到較低的成本消耗。
第一顆晶片實現一個以PLL頻率暫態響應為基礎的展頻方法。提出的展頻架構利用切換除數以達到迴路頻率改變的效果，藉由選擇適當的阻尼係數，迴路頻率會呈現三角波形的變化，並達到所需的EMI下降量。晶片量測的結果，EMI下降14.37dB，RMS jitter在鎖頻及展頻模式下分別為1.49ps及1.49ps，峰對峰jitter則分別為13.33ps及19.90ps。 第二顆晶片實現一個解展頻的方法，將時脈從展頻訊號解出而不需額外石英振盪器。所提出的解展頻架構使用調變頻率校正電路及三角波相位延遲校正電路，調變頻率合成器的除數以抵消展頻調變，藉此達到解展頻的效果。 | zh_TW |
| dc.description.abstract | This thesis focuses on the research of a spread-spectrum method as well as a de-spreading method. Two topics of these chips are named as an all-digital spread-spectrum clock generator with self-calibrated bandwidth and an all-digital de-spreading clock generator for DisplayPort. They are both fabricated in a 0.18um CMOS process and implemented in an all-digital manner. In contrast to those area-consuming analog filter implementation, these proposed circuits implement the necessary filtering function in a digital way, which achieve a low-cost solution owing to the high density of modern CMOS processes.
The first chip is to realize the proposed spread-spectrum method without the accompanist of DSM quantization noise, which based on the frequency transient response of a PLL. In proposed SSCG, division ratio switching has been chosen as a manner to give the PLL loop a frequency step. By selecting a damping ratio properly, the transient frequency will have a triangular profile in time-domain and has an adequate EMI reduction. The measured EMI reduction of proposed SSCG is 14.37dB, where the RMS jitter is 1.49ps in locked mode and 1.49ps in spread mode. Also the peak-to-peak jitter is 13.33ps in locked mode and 19.90ps in spread mode. The second chip is to implement the de-spreading technique, which regenerates a clock from a spread-spectrum clock reference without an extra crystal. The proposed crystal-less DSCG modulates the divided value of frequency synthesizer in order to cancel the spread-spectrum modulation, which is implemented by using a modulation frequency calibration and a triangular-wave phase delay calibration. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:15:59Z (GMT). No. of bitstreams: 1 ntu-101-R97943171-1.pdf: 6218433 bytes, checksum: df1806821fa474cbf422efd3f86e1377 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES xi LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Benefits of Digitizing PLLs 1 1.2 Spread-Spectrum Technique 2 1.2.1 Application of SSCGs 2 1.2.2 Different types of SSCGs 3 1.2.3 Motivation 5 1.2.4 Overview of proposed ADSSCG 6 1.3 De-Spreading Technique 8 1.3.1 Application of De-spreading 8 1.3.2 Motivation 10 1.3.3 Overview of proposed DSCG 10 1.4 Thesis organization 12 Chapter 2 A Design Procedure for All-Digital Phase-Locked Loops 15 2.1 Overview of Phase-Locked Loop 15 2.1.1 Phase-Locked Loop Basics 15 2.1.2 An Integer-N Frequency Synthesizer 16 2.1.3 A Fractional -N Frequency Synthesizer 17 2.2 Overview of All Digital PLLs 18 2.2.1 All Digital Phase-Locked Loop building blocks 18 2.2.2 A Phase-to-Digital Converter 19 2.2.3 A Vernier TDC 20 2.2.4 Digital Delta-Sigma Modulator 21 2.3 Model of ADPLL building blocks 22 2.3.1 Model of a P2D 22 2.3.2 Model of a first-order DLF 23 2.3.3 Model of a DCO 25 2.3.4 Model of a first-order DSM 25 2.3.5 Model of a MASH 1-1-1 DSM 26 2.3.6 Overall All-Digital PLL Model 27 2.4 Parameters Analysis for a Second-Order ADPLL 28 2.4.1 S-domain Linear Model for an ADPLL 28 2.4.2 Analysis of a second-order CPPLL 31 2.4.3 Analysis of a second-order ADPLL 33 2.5 Noise Analysis for an ADPLL 36 2.5.1 Overview of major noise sources in ADPLLs 36 2.5.2 Derivation of Noise Transfer Function 37 2.5.3 Noise Analysis of a TDC 40 2.5.4 Noise Analysis of a DCO 41 2.5.5 Noise Analysis of a Divider DSM 43 2.5.6 Overall Phase Noise Calculation 44 Chapter 3 An All-Digital SSCG with Self-Calibrated Bandwidth 49 3.1 Introduction 49 3.2 Spread-spectrum technique 51 3.2.1 Time-domain response in PLLs 51 3.2.2 Principle of proposed spread-spectrum technique 53 3.2.3 SSCG specification for SATA 55 3.2.4 SSCG Design Value Calculation 56 3.3 Circuit Description of Proposed ADSSCG 60 3.3.1 Proposed All-Digital SSCG Architecture 60 3.3.2 Phase Frequency Detector 62 3.3.3 Phase Selector 62 3.3.4 Coarse Fine Time-to-Digital Converter 64 3.3.5 Digitally-Controlled Oscillator 69 3.3.6 Fractional Dual-Modulus Divider 70 3.4 Proposed Bandwidth Calibration 74 3.4.1 Principle of Proposed Bandwidth Calibration 74 3.4.2 Bandwidth Calibration Method 78 3.5 Measurement 84 3.5.1 Measurement Environment 84 3.5.2 Die Photo 86 3.5.3 Measurement Result 86 3.5.4 Bandwidth Calibration Result 89 Chapter 4 An All-Digital De-Spreading Clock Generator for DisplayPort 91 4.1 Introduction 91 4.2 De-Spreading Technique 91 4.2.1 Frequency cancellation of an ADPLL 92 4.2.2 Principle of proposed de-spreading technique 93 4.2.3 DSCG Design Value Calculation 97 4.2.4 The triangular-wave division ratio design for DSCG 97 4.3 Proposed DSCG architecture 100 4.3.1 Proposed All-Digital DSCG Architecture 100 4.3.2 Multi-modulus divider 101 4.3.3 A digital MASH 1-1-1 DSM 103 4.4 De-spreading Calibration Circuit 104 4.4.1 Modulation frequency calibration 105 4.4.2 Triangular-wave phase delay calibration 108 4.5 Simulation of DSCG 113 4.5.1 Behavior simulation by Simulink 113 4.5.2 Transistor-level simulation by HSPICE 116 4.5.3 Specification and layout 116 Chapter 5 Conclusion 119 5.1 Thesis Summary 119 5.1.1 Summary of proposed SSCG 119 5.1.2 Summary of proposed DSCG 122 REFERENCE 125 | |
| dc.language.iso | en | |
| dc.title | 具有自我迴路頻寬校正之全數位展頻時脈產生器與解展頻時脈產生器 | zh_TW |
| dc.title | All-Digital Spread Spectrum Clock Generator with Self-Calibrated Bandwidth and De-Spreading Clock Generator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),陳巍仁(Wei-Zen Chen),黃柏鈞(Po-Chiun Huang),楊清淵(Ching-Yuan Yang) | |
| dc.subject.keyword | 全數位鎖相迴路,展頻時脈產生器,除小數頻率合成器,時間數位轉換器,三角積分調變器, | zh_TW |
| dc.subject.keyword | All-digital phase-locked loop (ADPLL),spread spectrum clock generator (SSCG),fractional-N frequency synthesizer,time-to-digital converter (TDC),digital delta-sigma modulator (DSM), | en |
| dc.relation.page | 128 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-02-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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