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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16427完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Ruei-Chi Shen | en |
| dc.contributor.author | 沈睿騏 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:14:27Z | - |
| dc.date.copyright | 2012-06-27 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-05-24 | |
| dc.identifier.citation | [1] Neil H. E. Weste and David Money Harris, Integrated Circuit Design, 4th Edition, Pearson, 2011.
[2] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, 1 ed. Norwell, MA and AH Dordrecht, The Netherlands: Kluwer Academic Publishers,1995. [3] K. Pagiamtzis and A. Sheikholeslami, 'Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,' IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006. [4] C.-S. Lin, J.-C. Chang, and B.-D. Liu, 'A low-power precomputation-based fully parallel content-addressable memory,' IEEE Journal of Solid-State Circuits, vol.38, no. 4, pp. 654-662, Apr. 2003. [5] S.-J. Ruan, C.-Y. Wu, and J.-Y. Hsieh, 'Low Power Design of Precomputation-Based Content-Addressable Memory,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 3, pp. 331-335, Mar. 2008. [6] C.-Y. Wu, S.-f. Ruan, C.-K. Cheng, and M.-B. Lin, 'A new Block-XOR precomputation-based CAM design for low-power embedded system,' in IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2005, pp.1-4. [7] J.-Y. Hsieh and S.-J. Ruan, 'Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm,' in Asia and South Pacific Design Automation Conference (ASPDAC), 2008, pp. 316-321. [8] T.-S. Lai, 'Local Grouping Algorithm for Synthesizing Low-Cost Parameter Extractor of Low-Power Pre-computation-Based Content Addressable Memory,' M.S. thesis, National Taiwan University, Taipei, 2008. [9] T.-S. Lai, C.-H. Peng, and F.-P. Lai, “Data Driven Approach for Low-Power Pre-Computation-Based Content Addressable Memory,” in IEEE Symposium on Computers & Informatics (ISCI), Mar. 2011, pp. 328-333. [10] “http://www.synopsys.com/home.aspx,” 15 Jan. 2011. [11] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, “MiBench: A free, commercially representative embedded benchmark suite,” in IEEE International Workshop on Workload Characterization (WWC-4), Dec. 2001, pp. 3-14. [12] “http://www.simplescalar.com/,” 10 Jan. 2011. [13] “http://cad.ee.ntu.edu.tw/,” 1 Jun. 2009. [14] “http://en.wikipedia.org/wiki/Standard_deviation,” [15] J.-H. Lee, G.-h. Park, S.-B. Park, and S.-D. Kim, 'A selective filter-bank TLB system [embedded processor MMU for low power],' in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 312-317. [16] K. J. Schultz, 'Content-addressable memory core cells: a survey,' Integration, the VLSI Journal vol. 23, no. 2, pp. 171-188, Nov. 1997. [17] I. Arsovski and A. Sheikholeslami, 'A current-saving match-line sensing scheme for content-addressable memories,' in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2003, pp. 304-494 vol.1. [18] C. A. Zukowski and S.-Y. Wang, 'Use of selective precharge for low-power content-addressable memories,' in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 1997, pp. 1788-1791 vol.3. [19] Jaeger and Blalock, Microelectronic Circuit Design, 4th Edition, McGraw Hill,2010. [20] A. P. Chandrakasan and R. W. Brodersen, 'Minimizing power consumption in digital CMOS circuits,' Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995. [21] K. Pagiamtzis and A. Sheikholeslami, 'A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,' IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004. [22] P. Echeverria, J. L. Ayala, and M. Lopez-Vallejo, 'A banked precomputation-based CAM architecture for low-power storage-demanding applications,' in IEEE Mediterranean Electrotechnical Conference (MELECON), 2006, pp. 57-60. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16427 | - |
| dc.description.abstract | 內容可定址記憶體常見於需要高速搜尋比對應用當中，例如網路路由器、虛擬記憶體所使用的轉譯後備緩衝區、霍夫曼解碼與離散餘弦轉換等。由於其具備高速平行搜尋的操作特性，故所消耗的功率往往亦相當鉅額。本篇論文提出了低功率內容可定址記憶體的合成方法，並透過在預先計算區塊中引入離散均勻分布的概念，以驗證其在不同方式下所合成之適應性參數萃取器，對於整體內容可定址記憶體所能減少功率消耗的分析。故使用此方法可有效地預測功率消耗的趨勢，並指出在特定資料下，所能減少功率消耗的極佳適應性合成方式，以期達成低功率內容可定址記憶體的設計目標。根據實驗結果顯示，相較於原先參數萃取器，本篇論文提出的方法至少可降低29%的功率消耗。 | zh_TW |
| dc.description.abstract | Content addressable memory (CAM) is often used in many applications which require searching in high speed such as network router, translation look-aside buffer (TLB), Huffman decoding, discrete cosine transform or the applications having quick lookup table operation. Due to its operational characteristic of parallel data searching, the power consumption is also exacerbated. In this thesis, a methodology was proposed for synthesizing a low power pre-computation-based content addressable memory (PB-CAM) effectively. The concept of discrete uniform distribution is adopted in pre-computation block so as to verify the outcomes of power reduction when the adaptive parameter extractors are synthesized in a different manner. With our proposed approach, we are able to estimate the tendency towards power consumption efficiently and determine which type of parameter extractor is superior in power reduction for the specific data. Experiments show that the power consumption of our approach is better by at least 29% compared with original parameter extractors. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:14:27Z (GMT). No. of bitstreams: 1 ntu-101-R98942080-1.pdf: 1382541 bytes, checksum: d2deb2dacb2da0ea883002e25a6463ef (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Definitions of Power 1 1.2 Sources of Power Dissipation 2 1.2.1 Dynamic Power 2 1.2.2 Static Power 4 1.3 Content Addressable Memory 5 1.3.1 Overview 5 1.3.2 Applications 7 1.4 Thesis Organization 9 Chapter 2 CAM Basics and Related Works 10 2.1 CAM Cell 10 2.1.1 Write Operation of a CAM Cell 11 2.1.2 Read operation of a CAM cell 12 2.2 Search Mechanism 13 2.3 Matchline Structure 15 2.3.1 NOR Matchline 16 2.3.2 NAND Matchline 16 2.3.3 Comparison 17 2.4 CAM Related Research 18 Chapter 3 Low Power Estimation Approach 20 3.1 One’s Count Scheme 20 3.2 Block-XOR Scheme 26 3.3 Gate-Block selection Algorithm 28 3.4 Discard and Interlaced Method 31 3.5 Proposed Estimation Approach 33 Chapter 4 Experimental Results 43 Chapter 5 Conclusion 50 REFERENCE 51 | |
| dc.language.iso | en | |
| dc.subject | 預測方法 | zh_TW |
| dc.subject | 低功率內容可定址記憶體 | zh_TW |
| dc.subject | 參數萃取器 | zh_TW |
| dc.subject | 預先計算 | zh_TW |
| dc.subject | 編碼 | zh_TW |
| dc.subject | estimation approach | en |
| dc.subject | low power PB-CAM | en |
| dc.subject | parameter extractor | en |
| dc.subject | pre-computation | en |
| dc.subject | coding | en |
| dc.title | 低功率預先計算為基礎的內容可定址記憶體之設計預估方法 | zh_TW |
| dc.title | An Estimation Approach for the Low Power Precomputation-Based Content-Addressable Memory Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 莊仁輝,李鴻璋 | |
| dc.subject.keyword | 低功率內容可定址記憶體,參數萃取器,預先計算,編碼,預測方法, | zh_TW |
| dc.subject.keyword | low power PB-CAM,parameter extractor,pre-computation,coding,estimation approach, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-05-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-101-1.pdf 未授權公開取用 | 1.35 MB | Adobe PDF |
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