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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Tsung-Han Lee | en |
dc.contributor.author | 李宗翰 | zh_TW |
dc.date.accessioned | 2021-06-07T18:12:05Z | - |
dc.date.copyright | 2012-07-16 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-06-27 | |
dc.identifier.citation | [1] R. E. Best, “Phase-locked loops: theory, design and applications,” 2nd edition, New York: McGraw-Hill, 1993
[2] B. Razavi, “Design of analog CMOS integrated circuits,” New York: McGraw -Hill, 2001. [3] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sep. 2004. [4] N. D. Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 52, pp. 505-509, Jan. 2005. [5] V. Kratyuk, “Digital phase-locked loops for multi-GHz clock generation,” PhD Dissertation, Oregon State University, Dec. 2006. [6] C. M. Hsu, “Techniques for high-performance digital frequency synthesis and phase control,” PhD Dissertation, Massachusetts Institute of Technology, Sep. 2008. [7] R. B. Staszewski and P. T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS,” John Wiley & Sons, Inc., 2006 [8] K. Fukuda, H. Yamashita, F. Yuki, G. Ono, R. Nemoto, E. Suzuki, T. Takemoto, and T. Saito, “10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 186–187. [9] M. H. Perrott, Y. Huang, R. T. Baird, B. W. Garlepp, D. Pastorello, E. T. King, Q. Yu, D. B. Kasha, P. Steiner, L. Zhang, J. Hein, and B. Del Signore, “A 2.5-Gb/s Multi-Rate 0.25-_m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition,” in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2930–2944. [10] B. S. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B. W. Gariepp, C. W. Werner, N. Nguyen, V. Stojanovic, and J. L. Zerbe, “A 7.5Gb/s 10-tap DFE receiver with first tap partial response, spectrally gated adaptation, and 2nd-order data-filtered CDR,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 228–229. [11] R. B. Staszewski, J. L. Wallberg, S. Rezeq, C. M. Hung, O. E. Eliezer, S. Vemulapalli, K. C. Fernando, K. Maggio, R. Staszewski, N. Barton, M. C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phone,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005. [12] M. Ferriss and M. P. Flynn, “A 14 mW fractional-N PLL modulator with an enhanced digital phase detector and frequency switching scheme,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 352–353. [13] H. H. Chang, P. Y. Wang, J. H. C. Zhan, and B. Y. Hsieh, “A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 200–201. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16377 | - |
dc.description.abstract | 隨著製程越來越進步的關係,類比電路在更進階的製程將會遇到很多的問題像是漏電流或是製程飄移等等,為了解決傳統的類比電路所遇到的問題,在鎖相迴路的領域內,全數位鎖相迴路已經變成一個當紅的研究方向。跟傳統的電流汞鎖相迴路架構相比,全數位鎖相迴路的優點例如容易製程轉移、面積消耗則因為沒有大量被動元件的濾波器而變小、功率上也是因為類比電路大幅被數位電路所取代而較小、在先進製程的高效能電路成果表現以及易與數位電路系統整合等好處。
但是使用全數位鎖相迴路卻也會衍生一些問題出來,其中像是時間數位轉換器被廣泛的運用在的全數位鎖相迴路,但是這個電路卻有著不線性、面積跟功耗都不低等缺點。為了解決傳統的時間數位轉換器的問題,在這次論文中,提出了相位數位轉換器取代傳統的時間數位轉換器的想法,利用一階的三角積分器來將量化雜訊雜訊重整到更高頻的地方並且利用數位濾波器將高頻雜訊去除,此外這個電路還有低功耗跟小面積的好處。另外一個想法則是使用類比的一階三角積分調變器去增加數位調控振盪器的解析度,跟傳統的方式相比,在同樣的超取樣率可以得到更佳的解析度。這顆晶片使用90奈米的互補式金氧半場效電晶體製程,其輸出頻率由4.8~6GHz,功率消耗為18mW,晶片核心面積為0.36mm2。 | zh_TW |
dc.description.abstract | An all-digital phase-locked loop (ADPLL) has recently become more and more popular since it turns into an attractive alternative to a conventional analog phase-locked loop (PLL). Compared with the conventional charge-pump PLL, the advantages of an ADPLL are smaller area and power consumption, easier process-upgrading, higher performance in the advanced process, and better integrity in digital system.
The time-to-digital converter (TDC) is widely used in the ADPLL, but it has some disadvantages such as non-linearity, higher area and power consumption. We propose a phase-to-digital converter (PDC) with first-order quantization noise shaping to replace the TDC in this chip. It has better linearity and lower cost than TDC. We also propose an analog delta-sigma modulator (DSM) to increase the resolution of a digitally-controlled oscillator (DCO). It can get better resolution in the same oversample ratio than the conventional digital DSM. This chip is fabricated in the 90nm CMOS process. Its power consumption is 18mW and core area is 0.36mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T18:12:05Z (GMT). No. of bitstreams: 1 ntu-101-R97943119-1.pdf: 4953107 bytes, checksum: 4aa3fedbc2b2f9fd1b3489cf85031c15 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 摘要 i
Abstract iii Contents v List of Figures vii List of Tables ix Chapter 1 序論 1 1.1 研究動機 1 1.2 論文架構 2 Chapter 2 全數位頻率合成器之概要 3 2.1 鎖相迴路概要 3 2.2 全數位鎖相迴路之分析 6 2.2.1 相位數位轉換器之線性模型 6 2.2.2 數位濾波器之線性模型 8 2.2.3 數位控制振盪器之線性模型 9 2.3 全數位鎖相迴路參數之計算 10 2.3.1 全數位鎖相迴路參數之設計流程 11 2.3.2 全數位鎖相迴路參數設計例子 12 2.4 結論 14 Chapter 3 使用相位數位轉換器之全數位頻率合成器 15 3.1 研究動機 15 3.2 電路架構 16 3.2.1 相位頻率偵測器 (phase frequency detector, PFD) 17 3.2.2 時間數位轉換器 (time-to-digital converter, TDC) 18 3.2.3 相位數位轉換器 (phase-to-digital converter, PDC) 21 3.2.4 數位控制振盪器 (Digitally-Controlled Oscillator, DCO) 27 3.2.5 類比一階三角積分器 (Analog first-order delta-sigma modulator) 29 3.2.6 數位濾波器 (Digital loop filter, DLF) 31 3.2.7 多模除數除頻器 (Multi-modulus divider) 33 3.2.8 數位二階MASH1-1三角積分器(Digital second-order MASH 1-1 delta-sigma modulator) 34 3.3 量測結果 35 3.4 結論以及文獻比較 44 Chapter 4 研究結論 47 Bibliography 49 | |
dc.language.iso | zh-TW | |
dc.title | 一個4.8~6十億赫茲應用於軟體無線收發器之全數位除小數頻率合成器 | zh_TW |
dc.title | A 4.8~6GHz All-Digital Fractional-N Frequency Synthesizer for Software-defined Radio | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),楊清淵(Ching-Yuan Yang),陳巍仁(Wei-Zen Chen),鄭國興(Kuo-Hsing Cheng) | |
dc.subject.keyword | 全數位除小數頻率合成器,相位數位轉換器,一階三角積分器, | zh_TW |
dc.subject.keyword | all-digital fractional-N frequency synthesizer,phase-to-digital converter,first-order delta-sigma modulator, | en |
dc.relation.page | 50 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-06-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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