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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Pang-Kai Liu | en |
dc.contributor.author | 劉邦楷 | zh_TW |
dc.date.accessioned | 2021-06-07T18:09:26Z | - |
dc.date.copyright | 2012-07-18 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-07-11 | |
dc.identifier.citation | [1] “HomePlug AV specification version 1.1,” HomePlug Powerline Alliance, May 2007.
[2] “HomePlug AV white paper,” HomePlug Powerline Alliance, 2005. [3] T. Piessens and M. Steyaert, “SOPA: A high-efficiency line driver in 0.35μm CMOS using a self-oscillating power amplifier,” IEEE ISSCC Dig. Tech. Papers, pp. 306-307, 457, Feb. 2001. [4] K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, “Three-stage large capacitive load amplifier with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000. [5] K. N. Leung and P. K. T. Mok, “Analysis of multistage amplifier-frequency compensation,” IEEE Trans. Circuits Syst. I, vol. 48, no. 9, pp. 1041-1056, Sept. 2001. [6] K. N. Leung and P. K. T. Mok, “Nested Miller compensation in low-power CMOS design,” IEEE Trans. Circuits Syst. II, vol. 48, no. 4, pp. 388-394, April 2001. [7] J. Pierdomenico, S. Wurcer, and B. Day, “A 684-mW adaptive supply full-rate ADSL CO driver,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1831-1838, Dec. 2002. [8] K. Findlater, T. Bailey, A. Bofill, N. Calder, S. Danesh, R. Henderson, W. Holland, J. Hurwitz, S. Maughan, A. Sutherland, and E. Watt, “A 90nm CMOS dual-channel powerline communication AFE for Homeplug AV with a Gb extension,” IEEE ISSCC Dig. Tech. Papers, pp. 464-628, Feb. 2008. [9] J. David Irwin and R. Mark Nelms, Basic Engineering Circuit Analysis, 8th edition, John Wiley & Sons, 2005. [10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [11] AD8398A data sheet, Single port VDSL2 line driver with shutdown, Analog Devices, Inc. [12] A. Bicakci, C.-S. Kim, and S.-S. Lee, “A CMOS line driver for ADSL central office applications,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2201-2208, Dec. 2003. [13] N. Weling, “Expedient permanent PSD reduction table as mitigation method to protect radio services,” IEEE International Symposium on Power Line Communications and Its Applications (ISPLC), pp. 305-310, April 2011. [14] M. Tlich, R. Razafferson, G. Avril, and A. Zeddam, “Outline about the EMC properties and throughputs of the PLC systems up to 100 MHz,” IEEE International Symposium on Power Line Communications and Its Applications (ISPLC), pp. 259-262, April 2008 [15] H. Casier, P. Wouters, B. Graindourze, and D. Sallaerts, “A 3.3-V, low-distortion ISDN line driver with a novel quiescent current control circuit,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1130-1133, July 1998. [16] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th edition, Oxford University Press, 2004. [17] A. N. Mohieldin, E. Sanchez-Sinencio, and J. Silva-Martinez, “A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 663-668, April 2003. [18] C. Lujan-Martinez, R. G. Carvajal, J. Galan, A. Torralba, J. Ramirez-Angulo, and A. Lopez-Martin, “A tunable pseudo-differential OTA with -78 dB THD consuming 1.25 mW,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 527-531, June 2008. [19] V. Dhanasekaran, J. Silva-Martinez, and E. Sanchez-Sinencio, “Design of three-stage class-AB 16 Ω headphone driver capable of handling wide range of load capacitance, ” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1734-1744, June 2009. [20] D. M. Monticelli, “A quad CMOS single-supply op amp with rail-to-rail output swing,” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1026-1034, Dec. 1986. [21] Xicheng Jiang, Jungwoo Song, T. L. Brooks, Jianlong Chen, V. Chandrasekar, F. Cheung, S. Galal, D. Cheung, G. C. Ahn and M. Bonu, “A 10mW stereo audio CODEC in 0.13μm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 82-83, Feb. 2010. [22] G. Cesura, A. Bosi, F. Rezzi, R. Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, O. Carnu, and T. Cho, “A VDSL2 CPE AFE in 0.15μm CMOS with integrated line driver,” IEEE ISSCC Dig. Tech. Papers, pp. 108-109,109a, Feb. 2009. [23] M. S. Kappes, “A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 371-376, March 2000. [24] C.-Y. Cha and S.-G. Lee, “A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 669-672, April 2003. [25] H.-H. Hsieh, J.-H. Wang, and L.-H. Lu, “Gain-enhancement techniques for CMOS folded cascode LNAs at low-voltage operations,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1807-1816, Aug. 2008. [26] E. Seevinck and R. J. Wiegerink, “Generalized translinear circuit principle,” IEEE J. Solid-State Circuits, vol. 26, no. 8, pp. 1098-1102, Aug. 1991. [27] B. A. Minch, “MOS translinear principle for all inversion levels,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 121-125, Feb. 2008. [28] R. Mahadevan and D. A. Johns, “A differential 160-MHz self-terminating adaptive CMOS line driver,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1889-1894, Dec. 2000. [29] K. Hadidi, H. Oshima, M. Sasaki and T. Matsumoto, “A highly linear fully differential low power CMOS line driver, ” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 541-544, Sept. 2003. [30] Stephen J. Chapman, Electric Machinery Fundamentals, 4th edition, McGraw-Hill, 2005. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16315 | - |
dc.description.abstract | 為實現數位家庭的願景,高速的家用通訊網路是不可或缺的。為達成此目標,利用電力線來傳輸寬頻訊號可節省額外佈線的成本。而本研究在提升資料傳輸量上將頻帶從HomePlug AV1規格的2-28MHz拓展到2-60MHz。
世界上的各種電力線其特性不盡相同,由於電力線的效應讓線驅動器所看到的負載並非一致。本研究使用阻尼網路電路與基極電阻來消除在開迴路頻率響產生的高頻凸起,並在電阻性負載改變的時候高頻凸起亦能被抑制。 本研究在TSMC 0.18μm CMOS製程下實現一個電力線通訊系統之線驅動器,供應電壓為2.5V,在總諧波失真的量測中使用1:1的變壓器來進行量測。而總諧波失真的量測結果在60MHz與3.02Vpp的情形下約是-38.8dB。此外,在多音功率比的量測中使用1:4的變壓器,並分別量測線驅動器驅動同軸電纜線與5公尺電力線的情形。在驅動同軸電纜線的情形下,其頻帶外多音功率比大於22dBc,輸出功率為5.90dBm,峰均比為5.0。頻帶內多音功率比大於47dBc,輸出功率為5.83dBm,峰均比為5.0。在驅動5公尺電力線的情形下,其頻帶外多音功率比大於27dBc,輸出功率為5.22dBm,峰均比為4.6。而頻帶內多音功率比大於52dBc,輸出功率為5.15dBm,峰均比為4.4。 | zh_TW |
dc.description.abstract | The high speed communication network in home is indispensable to achieve the vision of digital home. In order to achieve the goal, transmitting data through powerline is adopted since it saves the cost of extra cable setups. Moreover, to improve the data rate, the bandwidth is increased from the 2-28MHz HomePlug AV1 specification to the 2-60MHz in this study.
The characteristics of powerline are different everywhere in the world. Moreover, the loading which is seen by the line driver varies due to the powerline effects. The damping network circuit and the body resistor are used in this study to suppress the open loop high frequency peaking effect. As a result, the peaking effect is suppressed even when the resistive loading changes. The line driver of the powerline communication is realized in TSMC 0.18μm CMOS process. Moreover, the supply voltage of the proposed line driver is 2.5V. The total harmonic distortion (THD) is measured with the 1:1 transformer. The THD measurement result of the 60 MHz, 3.02Vpp output signal is about -38.8dB. In addition, the multi-tone power ratio (MTPR) measurements of the line driver are done with the 1:4 transformer. The proposed line driver which drives the coaxial cable and the 5 meter powerline cable are measured respectively. In the coaxial cable measurement situation, the out of band MTPR is better than 22dBc with 5.90dBm output power and 5.0 PAR. Moreover, the in-band MTPR is better than 47dBc with 5.83dBm output power and 5.0 PAR. In the 5 meter powerline cable measurement situation, the out of band MTPR is better than 27dBc with 5.22dBm output power and 4.6 PAR. Furthermore, the in-band MTPR is better than 52dBc with 5.15dBm output power and 4.4 PAR. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T18:09:26Z (GMT). No. of bitstreams: 1 ntu-101-R97943012-1.pdf: 5326151 bytes, checksum: eb4344d1b92130e909bb1849ef731ac0 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 口試委員會審定書(中文) i
口試委員會審定書(英文) iii 誌謝 v 中文摘要 vii Abstract ix Contents xi List of Figures xv List of Tables xxi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 2 Chapter 2 Basic Concepts of Line Driver 3 2.1 The Transmission Channel: Powerlines 3 2.1.1 Variation of the Powerline Characteristics 4 2.2 Multi-Tone Signals in Powerline Communication 5 2.2.1 Peak to Average Ratio 5 2.3 Voltage Headroom and the Transformer 6 2.4 Linearity Considerations 8 2.4.1 PLC Spectrum Consideration 9 2.4.2 High Frequency Extension Band 9 2.4.3 MTPR Testing in This Study 10 2.5 Line Driver Specification 10 Chapter 3 Proposed Line Driver 11 3.1 Close Loop Circuitry of the Line Driver 11 3.2 Pseudo-Differential Operational Amplifier 12 3.2.1 First Stage Amplifier 12 3.2.2 Second Stage with the Damping Network 13 3.2.3 Class AB Control Stage and Output Stage 14 3.2.4 Half Circuit of Proposed Pseudo-Differential Operational Amplifier 15 3.2.5 Close Loop Line Driver Class AB Operation 16 3.2.6 Bias Generation Circuits of First Stage and Second Stage 16 3.2.7 Bias Generation Circuit of Class AB Control Stage 17 3.3 AC Simulation Results 18 3.3.1 Peaking Effect of the Open Loop Frequency Response 18 3.3.2 Open Loop Frequency Response 20 3.3.3 Close Loop Frequency Response 21 3.4 Transient Simulation Results of Close Loop Line Driver 23 Chapter 4 THD Measurement Results 25 4.1 The Single Tone Measurements 25 4.1.1 The Single Tone Measurement Setups 27 4.2 The 10MHz measurements 28 4.3 The 20MHz Measurements 29 4.4 The 30MHz Measurements 31 4.5 The 40MHz Measurements 32 4.6 The 50MHz Measurements 34 4.7 The 60MHz Measurements 35 4.8 THD Measurement Conclusions 37 4.8.1 Oscillation 37 4.8.2 THD Measurements Comparison 38 Chapter 5 MTPR Measurement Results 39 5.1 MTPR Measurement Setups 39 5.2 Oscillation Consideration 40 5.3 Coaxial Cable MTPR Measurement Results 41 5.3.1 Spectrum of Out of Band MTPR with Coaxial Cable 41 5.3.2 PAR of the Out of Band MTPR with Coaxial Cable 42 5.3.3 Out of Band MTPR Measurements with Coaxial Cable 43 5.3.4 Spectrum of In-Band MTPR with Coaxial Cable 44 5.3.5 PAR of In-Band MTPR with Coaxial Cable 45 5.3.6 In-Band MTPR Measurements with Coaxial Cable 46 5.4 Powerline Cable MTPR Measurement Results 48 5.4.1 Spectrum of Out of Band MTPR with Powerline 48 5.4.2 PAR of the Out of Band MTPR with Powerline 49 5.4.3 Out of Band MTPR Measurements with Powerline 50 5.4.4 Spectrum of In-Band MTPR with Powerline 52 5.4.5 PAR of In-Band MTPR with Powerline 52 5.4.6 In-Band MTPR Measurements with Powerline 53 5.5 MTPR Measurements Comparison 56 Chapter 6 Conclusions 57 References 59 | |
dc.language.iso | en | |
dc.title | 適用於電力線通訊系統之線驅動器設計 | zh_TW |
dc.title | A Line Driver Design for Powerline Communication Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 闕志達(Tzi-Dar Chiueh),林宗賢(Tsung-Hsien Lin),張順志(Soon-Jyh Chang),陳科宏(Ke-Horng Chen) | |
dc.subject.keyword | 電力線通訊,線驅動器,變壓器,總諧波失真,多音功率比, | zh_TW |
dc.subject.keyword | powerline communication,line driver,transformer,total harmonic distortion,multi-tone power ratio, | en |
dc.relation.page | 63 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-07-11 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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