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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭柏齡(Po-Ling Kuo) | |
dc.contributor.author | Yu-Shen Tien | en |
dc.contributor.author | 田鈺申 | zh_TW |
dc.date.accessioned | 2021-06-07T18:08:20Z | - |
dc.date.copyright | 2012-07-31 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-07-17 | |
dc.identifier.citation | [1] 李百祺, 醫用超音波原理, 2000.
[2] G. G. Yaralioglu, et al., 'Finite-element analysis of capacitive micromachined ultrasonic transducers,' Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on, vol. 52, pp. 2185-2198, 2005. [3] R. G. Pridham and R. A. Mucci, 'Digital interpolation beamforming for low-pass and bandpass signals,' Proceedings of the IEEE, vol. 67, pp. 904-919, 1979. [4] A. S. Ergun, et al., 'Capacitive micromachined ultrasonic transducers: Theory and technology,' Journal of Aerospace Engineering, vol. 16, p. 76, 2003. [5] Y. Tsuji, et al., 'Low temperature process for CMUT fabrication with wafer bonding technique,' 2010, pp. 551-554. [6] S. Wong, et al., 'Evaluation of wafer bonded CMUTs with rectangular membranes featuring high fill factor,' Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on, vol. 55, pp. 2053-2065, 2008. [7] O. Oralkan, et al., 'Capacitive micromachined ultrasonic transducers: Next-generation arrays for acoustic imaging?,' Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on, vol. 49, pp. 1596-1610, 2002. [8] C. B. Doody, et al., 'Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers,' Microelectromechanical Systems, Journal of, vol. 20, pp. 104-118, 2011. [9] P. K. Tang, et al., 'Design and characterization of the immersion-type capacitive ultrasonic sensors fabricated in a CMOS process,' Journal of Micromechanics and Microengineering, vol. 21, p. 025013, 2011. [10] Y. Huang, et al., 'Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology,' Microelectromechanical Systems, Journal of, vol. 12, pp. 128-137, 2003. [11] C. B. Doody, et al., 'Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers,' JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, vol. 20, 2011. [12] X. Rottenberg, et al., 'Consistent Analytical Model for Single and Dual Thickness Capacitive Micromachined Ultrasound Transducers (cMUT).' [13] S. Machida, et al., 'Analysis of the charging problem in capacitive micro-machined ultrasonic transducers,' 2008, pp. 383-385. [14] J. R. Reid, 'Simulation and measurement of dielectric charging in electrostatically actuated capacitive microwave switches,' 2002, pp. 250-256. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16289 | - |
dc.description.abstract | 本研究利用電容式微機電超音波換能器(CMUTs)原理,結合TSMC CMOS 0.35製程,開發一種新式電容式微機電超音波感測器(CMUS)。感測結構於CMOS晶圓底部階層製作,以多晶矽層作為結構犧牲層,搭配上部金屬十字交叉犧牲層設計。經由濕蝕刻後製程處理,成功釋放位於晶圓底部的電容式薄膜結構。另外結合底部金屬層的佈局,使感測器等效中空層間距減少,大幅度的降低感測器操作偏壓(0~5V)。
再者本研究提出一種介於犧牲層與蝕刻洞之間的新式蝕刻裝置:蝕刻槽。經由蝕刻槽使犧牲層露出的面積增加,有效地提高感測器後製程速度與良率。另一方面,搭配微小蝕刻洞(0.5μm×0.5μm)的使用,元件防水封裝製程可以輕易的完成,讓感測器的製作更加的穩定。 最後感測元件以打線的方式整合CMOS 0.18後端放大電路,完成超音波感測整合電路。此感測收電路有效地降低電路寄生電容並提高訊雜比。為了消除充電效應的影響,施加交流偏壓於感測電路進行量測。獲得訊雜比為45.54dB,頻寬比為112.88%以及中心頻為7.39MHz的量測結果。 | zh_TW |
dc.description.abstract | This paper presents a successful achievement on lowering bias voltage of CMUS (capacity micromachined ultrasound sensor). By using the TSMC CMOS 0.35 process and etching post-process the devices are fabricated on the CMOS chips bottom layers. Based on the CMUTs’ construct theory, we etch the top cross-metal layers and polysilicon layer to release the membrane. By polysilicon layer etching and adding contact as the part of top electrode, the equivalent gap will be reduced and the bias voltage will decrease obviously (0~5V).
Furthermore, we propose a novel structure between etching holes and sacrificial layer. The structure called etching ditch improves the etching rate and yield by exposing larger area when wet etching. On the other hand, the device will be easily water-proven due to the small size of etching hole (0.5um*0.5um) over the ditch. Also, by wire-bonding with CMOS ASIC fabricated in TSMC 0.18-μm CMOS process, the integrated sensing circuit reduces the parasitic capacitance and enhances the signal to noise ratio effectively. For reducing the charging effect of the devises, an alternating bias voltage is applied, and the characterization of CMOS-electronics shows the large fractional bandwidth (112.88%) and 45.54dB signal to noise ratio in the 7.39MHz resonant frequency. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T18:08:20Z (GMT). No. of bitstreams: 1 ntu-101-R99945049-1.pdf: 12338724 bytes, checksum: ef409c82804f6dbe4bc56c10a9bfdadf (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 誌謝 I
中文摘要 II ABSTRACT III CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XI Chapter 1 Introduction 1 1.1 前言 1 1.2 CMUT 架構 3 1.3 工作原理 4 1.4 CMUT半導體製作方式探討 5 1.4.1 體型微加工 6 1.4.2 面型微加工 9 1.5 研究動機 10 Chapter 2 CMUS 感測器原理與感測器設計 12 2.1 電容式感測器原理介紹 12 2.1.1 等效間距 13 2.1.2 崩潰電壓(Collapse Voltage) 14 2.1.3 電能機械能轉換常數(Electromechanical Coupling Coefficient) 16 2.2 CMOS MEMS 感測器結構設計 18 2.2.1 結構層設計 18 2.2.2 結構圖形設計 20 2.2.3 蝕刻槽設計 22 2.2.4 上部金屬十字交叉犧牲層設計 24 2.3 模擬結果分析 25 2.4 感測器結構佈局 34 2.5 感測器放大電路 35 Chapter 3 感測器元件後製程與結果 36 3.1 後製程步驟 36 3.2 後製程結果 39 3.2.1 金屬蝕刻製程 40 3.2.2 多晶矽蝕刻製程 43 3.2.3 雷射切割製程 45 3.2.4 Parylene-C沉積封膜 47 3.2.5 製程其它量測結果 48 Chapter 4 感測器特性量測結果 51 4.1 量測架設介紹 51 4.2 單一CMUS元件量測結果 53 4.2.1 Parylene-C厚度0.7μm元件量測 53 4.2.2 Parylene-C厚度1.2μm元件量測 55 4.3 CMUS與ASIC 整合電路量測結果 59 4.3.1 直流偏壓訊號量測 59 4.3.2 交流偏壓訊號量測 61 4.3.3 聲場與靈敏度量測 62 Chapter 5 結論與未來展望 67 5.1 結論 67 5.2 未來展望 69 REFERENCE 71 | |
dc.language.iso | zh-TW | |
dc.title | CMOS MEMS 低偏壓電容式超音波感測器開發 | zh_TW |
dc.title | Low Voltage CMOS MEMS Capacitive Micromachined Ultrasonic Sensors Development | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 李百祺(Pai-Chi Li),田維誠(Wei-Cheng Tian) | |
dc.contributor.oralexamcommittee | 呂良鴻(Liang-Hung Lu),劉建宏(Jian-Hung Liu) | |
dc.subject.keyword | CMUT,CMOS MEMS,蝕刻槽,充電效應,崩潰電壓, | zh_TW |
dc.subject.keyword | CMUT,CMOS MEMS,Etching Ditch,Charging Effect,Collapse Voltage, | en |
dc.relation.page | 71 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-07-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 生醫電子與資訊學研究所 | zh_TW |
顯示於系所單位: | 生醫電子與資訊學研究所 |
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