6H-矽碳及鍺之發光研究與三維積體電路及鰭式電晶體之應變場分析

Abstract

本論文包含二大部分，發光元件及應變矽技術，其中發光元件包含6H 矽碳 金氧半元件以及鍺金氧半與pn 接面元件，應變矽技術包含矽穿孔索造成之應變 以及SiGe 源�汲極在鰭式電晶體造成之應變。 6H 矽碳金氧半元件的發光頻譜來自於施體受體對的結合放光而非能隙躍遷 放光，空乏區中的電場可以幫助電子電洞於施體受體能階中跳躍而幫助放光。 鍺薄膜於矽基板上會產生錯位，而其產生之缺陷能階會降低間接能隙的光致 發光頻譜。鍺pn 接面元件之電致發光頻譜來自於塊材內部，而鍺金氧半元件來 自於氧化層與鍺之介面，其介面粗糙度散射可以提供動量守恆且增強間接能隙發 光頻譜。 矽穿孔製程溫度由200 oC 降至室溫，由於銅之熱膨脹係數大於矽而產生應 變，徑向為張應變而橫向為壓應變，n 型電晶體電流方向適合平行二矽穿孔支連 心線，而p 型電晶體適合垂直連心線，矽穿孔排列成六邊形或圓形可以降低保持 在外區。 SiGe 源�汲極於鰭式電晶體適合鬆弛邊界條件，在通道靠近源�汲極處有 最大壓應變，包住式SiGe 源�汲極比取代式SiGe 源�汲極產生更大壓應變。

There are two topics in this thesis including the light-emitting diodes and the strained Si techniques. The light-emitting diodes include the SiC MIS, the Ge MIS, and the Ge pn junction. The strained Si techniques include the strain induced by through Si vias and that induced by SiGe source/drain on FinFET. The electroluminescence of the SiC MIS is due to the donor and acceptor pairs instead of the band-edge transition. The electric field in the depletion assists the electrons and holes in hopping in the donor and acceptor levels to enhance the emission intensity, respectively. The dislocation of the Ge-on-Si leads to the defect levels reducing the indirect band-edge emission of the photoluminescence. The electroluminescence of the Ge pn junction and the Ge MIS is from the Ge bulk and the oxide/Ge interface, respectively. The roughness scattering at the oxide/Ge interface can conserve the momentum and enhance the indirect band-edge emission. The process temperature of the through Si vias from 200 oC cooling down to the room temperature with the larger coefficient of thermal expansion of the Cu than that of the Si leads to the strain. The strains along the radial direction and the angular direction are tensile and compressive, respectively. The current directions of the nMOS and pMOS favor to be parallel and vertical to the line of the through Si via III centers, respectively. The placement of through Si vias in a hexagon and in a circle can reduce the area of the keep-out zone. The relaxed surface boundary condition is applied suitably for the SiGe source/drain on the FinFET. There is the most compressive strain near the source/drain regions. The wrapped SiGe source/drain leads to more compressive strain than that by replaced one.