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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16130完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士(Shey-Shi Lu) | |
| dc.contributor.author | Han-Wen Chang | en |
| dc.contributor.author | 張瀚文 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:02:11Z | - |
| dc.date.copyright | 2012-08-15 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-03 | |
| dc.identifier.citation | [1] Thanapatay, D.; Suwansaroj, C.; Thanawattano, C.; , 'ECG beat classification method for ECG printout with Principle Components Analysis and Support Vector Machines,' Electronics and Information Engineering (ICEIE), 2010 International Conference On , vol.1, no., pp.V1-72-V1-75, 1-3 Aug. 2010
[2] Tee Hui Teo; Xinbo Qian; Kumar Gopalakrishnan, P.; Hwan, Y.S.; Haridas, K.; Chin Yann Pang; Hyouk-Kyu Cha; Minkyu Je; , 'A 700- W Wireless Sensor Node SoC for Continuous Real-Time Health Monitoring,' Solid-State Circuits, IEEE Journal of , vol.45, no.11, pp.2292-2299, Nov. 2010 [3] T. Hui Teo, G. K. Lim, D. S. David, K. H. Tan, P. K. Gopalakrishnan, and R. Singh, “Ultra low-power sensor node for wireless health monitoring system,” in Proc. IEEE Int. Symp. Circuits and Systems, May 2007, pp. 229–232. [4] Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu; , 'A 550- 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,' Solid-State Circuits, IEEE Journal of , vol.46, no.8, pp.1881-1892, Aug. 2011 [5] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 236–237. [6] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. IEEE ISCAS, 2005, pp. 184–187. [7] Hui Zhang; Yajie Qin; Siyu Yang; Zhiliang Hong; , 'Design of an ultra-low power SAR ADC for biomedical applications,' Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on , vol., no., pp.460-462, 1-4 Nov. 2010 [8] David A. Johns, Ken Martin, “Analog Integrated Circuit Design,” John Wiley & Sons, Inc. 1997. [9] B. Razvi, “Principles of Data Conversion System Design” IEEE Press 1995. [10] 張哲維, “Design and Application of Analog-to-Digital Converter,” National Taiwan University MS Thesis, July 2007. [11] 方柏翔, “Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters,” National Taiwan University MS Thesis, June 2009. [12] 許升睿, “The Design of Analog-to-Digital Converter for Bio-Medical Application,” National Taiwan University MS Thesis, July 2011. [13] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” , in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010, pp. 731-740 [14] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999. [15] S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1430–1440, Jul. 2008. [16] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 236–237. [17] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177. [18] B. P. Ginsburg and A. P. Chandrakasan, “Highly interleaved 5 b 250MS/s ADC with redundant channels in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 240–241. [19] Chen, S.-W.M.; Brodersen, R.W.; , 'A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- CMOS,' Solid-State Circuits, IEEE Journal of , vol.41, no.12, pp.2669-2680, Dec. 2006. [20] H. Hong and G. Lee, “A 65-fJ/conversion-step 0.9-V 200kS/s rail-to-rail 8-bit successive approximation ADC, ”IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007. [21] Hariprasath, V.; Guerber, J.; Lee, S.-H.; Moon, U.-K.; , 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' Electronics Letters , vol.46, no.9, pp.620-621, April 29 2010 [22] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; Chung-Ming Huang; Chih-Hao Huang; Linkai Bu; Chih-Chung Tsai; , 'A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,' Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.386-387, 7-11 Feb. 2010 [23] Tsung-Che Lu; Lan-Da Van; Chi-Sheng Lin; Chun-Ming Huang; , 'A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications,' Custom Integrated Circuits Conference (CICC), 2011 IEEE , vol., no., pp.1-4, 19-21 Sept. 2011 [24] H.–W. Chen, Y.-H. Lin, and H.-S. Chen “A 3mW 12b sub-range SAR ADC,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 153-156, Nov. 2009 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16130 | - |
| dc.description.abstract | 在世界各地的大多數已開發國家，人口老齡化是一個普遍觀察到的現象。我們的國家在數年後，也會看到此現象。而電機電子領域人將研究重點從消費性電子產品轉向生醫應用。在這個趨勢下，我們設計適合應用於生醫系統的類比數位轉換器。
在本論文的第四章，我們介紹一種利用單調式切換電容以減少功耗及採用MOM電容以縮小整體面積的連續漸進式類比數位轉換器。如此一來，我們可以使用更少的晶片面積卻達到和傳統電路一樣的解析度。 在本論文的第五章，我們介紹一種採用傳統架構的單端輸入連續漸進式類比數位轉換器。 在本論文的第六章，我們介紹一種採用第四章架構的優點非同步式控制邏輯及修改第五張的傳統單端架構以搭配二進制錯誤補償機制的單端輸入連續漸進式類比數位轉換器。 這些晶片都是使用TSMC 0.18um 1P6M CMOS的製程實現。 | zh_TW |
| dc.description.abstract | Ageing population is a commonly observed phenomenon in most developed countries all over the world. Our country may see the phenomenon in few years.
Electrical engineers have turned their attention from consumer products to application in biomedical. We design ADCs that are suitable for biomedical application under this trend. In Chapter 4 of this thesis, a low power dual mode SAR ADC is presented which uses monotonic switching procedure to decrease the power consumption and MOM capacitor array that makes the chip area smaller while get the same resolution as the traditional circuit. In Chapter 5 of this thesis, a low power single-ended SAR ADC is presented which uses conventional structure. In Chapter 6 of this thesis, a low power single-ended SAR ADC with binary-scaled error compensation is presented which uses the advantage of asynchronous control logic in Chapter 4 and modifies the structure in Chapter 5. These chips are fabricated by TSMC 0.18u, 1P6M CMOS technology and the measurement results will be shown. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:02:11Z (GMT). No. of bitstreams: 1 ntu-101-R99943050-1.pdf: 6248487 bytes, checksum: 5a4e5edb8ddd260dbf5b01ea9db35321 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 ECG Signal and System Requirement 3 2.1 ECG Signal Introduction [1] 3 2.2 A Wireless ECG Monitoring System [2] 4 2.3 Principle of Analog-to-Digital Converter Design 6 Chapter 3 The fundamentals of Analog-to-Digital Converters 11 3.1 Introduction 11 3.2 ADC Performance Metrics [8][9][10][11][12] 12 3.2.1 Static Specifications 13 3.2.2 Dynamic Specifications 16 3.3 Analog-to-Digital Converter Architectures 20 3.3.1 Flash Architecture 20 3.3.2 Two-Step Architecture 21 3.3.3 Pipelined Architecture 22 3.3.4 Successive Approximation Architecture 23 3.3.5 Delta-Sigma Architecture 24 3.4 Comparison of the ADCs 25 Chapter 4 A 1-V Low Power Dual mode 10-Bit SAR Analog-to-Digital Converter 27 4.1 Introduction 27 4.2 Fully-differential SAR ADC 28 4.2.1 Basic Operation Principle of Differential SAR ADC 28 4.2.2 Circuit Implementation of This Design 32 4.2.3 Circuit Building Blocks 35 4.2.4 Fully-differential SAR ADC Simulation Results 48 4.3 Single-ended SAR ADC 51 4.3.1 Basic Operation Principle of Single-ended SAR ADC 51 4.3.2 Circuit Implementation of This Design 54 4.3.3 Circuit Building Blocks 54 4.3.4 Single-ended SAR ADC Simulation Results 56 4.4 Measurement Result 59 4.4.1 The PCB Design 60 4.4.2 Measurement setup 61 4.4.3 The measurement of fully-differential SAR ADC 62 4.4.4 The measurement of single-ended SAR ADC 63 4.4.5 Measurement results of summary 65 4.4.6 Applications 66 Chapter 5 A 1-V Low Power 10-Bit SAR Analog-to-Digital Converter 67 5.1 introduction 67 5.2 Basic Operation Principle of SAR ADC 67 5.3 Circuit Implementation of This Design 71 5.4 Circuit Building Blocks 72 5.5 SAR ADC Simulation Results 80 5.6 Measurement Result 83 5.6.1 The PCB Design 84 5.6.2 Measurement setup 84 5.6.3 The measurement of fully-differential SAR ADC 85 5.6.4 Measurement results of summary 87 5.6.5 Applications 88 Chapter 6 A 1-V Low Power 10-Bit SAR Analog-to-Digital Converter with Binary-Scaled Error Compensation 89 6.1 introduction 89 6.2 Basic Operation Principle of SAR ADC 89 6.3 Circuit Implementation of This Design 93 6.4 Circuit Building Blocks 98 6.5 SAR ADC Simulation Results 107 6.6 Measurement Result 110 6.6.1 The PCB Design 111 6.6.2 Measurement setup 111 6.6.3 The measurement of SAR ADC 112 6.6.4 Measurement results of summary 114 Chapter 7 Conclusion 115 | |
| dc.language.iso | en | |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 低電壓 | zh_TW |
| dc.subject | low power | en |
| dc.subject | Successive approximation | en |
| dc.subject | low supply voltage | en |
| dc.subject | ADC | en |
| dc.title | 應用於心電訊號偵測系統之類比數位轉換器 | zh_TW |
| dc.title | A low power Analog-to-Digital Converter for ECG signal monitoring system application | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孟慶宗(Chin-Chun Men),孫台平(Tai-Ping Sun),林佑昇(Yo-Sheng Lin) | |
| dc.subject.keyword | 連續漸進式,類比數位轉換器,低功耗,低電壓, | zh_TW |
| dc.subject.keyword | Successive approximation,ADC,low power,low supply voltage, | en |
| dc.relation.page | 118 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-08-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-101-1.pdf 未授權公開取用 | 6.1 MB | Adobe PDF |
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