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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16083
標題: | 鎖相迴路和溫度補償振盪器 Phase-Locked Loops and Temperature Compensated Oscillator |
作者: | Peng-Sheng Chen 陳鵬升 |
指導教授: | 劉深淵 教授(Shen-Iuan Liu) |
關鍵字: | 鎖相迴路,溫度補償振盪器, Phase-Locked Loops,Temperature Compensated Oscillator, |
出版年 : | 2012 |
學位: | 碩士 |
摘要: | 鎖相迴路是混合訊號積體電路其中之關鍵電路,常應用於通訊、控制、儀器和感應器電路中。在此我們針對不同特色的鎖相迴路做設計及分析。
此論文主軸主要分為四個部份。第一部份實現了快速鎖定及低突波的鎖相迴路,我們加快高增益相位偵測器的鎖定時間並降低突波問題。藉由所提出的頻率偵測器,量測到的鎖定時間從原本的103.89us加快至3.89us。使用了所提出的抑制突波技術,量測到的突波改善了39dB。 第二部份實現0.4V 400MHz的鎖相迴路並提出了新穎的電路讓鎖相迴路在次臨界區操作。晶片包含完整的二階迴路濾波器下面積只有0.0143 mm2。消耗功率為9.2uW。 第三部份是針對低溫度係數數位控制振盪器之設計,並實現和分析正溫度和負溫度係數延遲單元。此外我們提出了轉導補償技術去達到更高的補償解析度。提出的數位控制振盪器在120度的溫度範圍中,模擬到10.26 ppm/℃的溫度係數。 第四部份提出0.5V 900MHz具有可適性電壓的鎖相迴路。可適性電壓不僅達到抵抗製程、電壓、和溫度的變化影響,更可達到較低功率消耗的優點。模擬消耗功率為42.15uW,面積為0.0228 mm2。 Phase-Locked Loops (PLLs) are one of the key building blocks in mixed-signal integrated circuits, and are essential in various fields including communications, controls, instrumentations and sensors. For this reason, we design and analyze various features of the PLL in this thesis. This thesis consists of four parts. The first part realizes a fast-locking and low spur PLL. Using high-gain phase detector, we enhance the locking time and improve the spur problem. The measured locking time is reduced from 103.89us to 3.89us with the proposed FD. The measured reference spur is improved by 39dB with the proposed spur suppression technique. The second part implements a 0.4V 400MHz PLL. We propose several novel circuits for PLL to operate in the sub-threshold region. The core area is only 0.0143 mm2 with an on-chip second-order loop filter. The power consumption is 9.2uW. The third part aims to design a low temperature coefficient digitally-controlled ring oscillator. Positive and negative temperature coefficient delay cell is employed and analyzed. Besides, we propose a transconductance compensated technique to achieve higher compensation resolution. The proposed DCRO temperature coefficient is achieved 10.26 ppm/℃ over 120℃ temperature range. The fourth part proposes a 0.5V 900MHz PLL with adaptive supply technique. The adaptive supply not only resists the process, voltage, and temperature variations, but also achieves lower power consumption. The simulated power consumption is 42.15uW and the core area is 0.0228 mm2. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16083 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-101-1.pdf 目前未授權公開取用 | 4.46 MB | Adobe PDF |
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