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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Li-Yuan Lee | en |
dc.contributor.author | 李立源 | zh_TW |
dc.date.accessioned | 2021-06-07T17:53:14Z | - |
dc.date.copyright | 2012-08-21 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-17 | |
dc.identifier.citation | [1] D. Kim, J. Kim, and C. Cho, “A 94GHz Locking Hysteresis-assisted and Tunable CML Static Divider In 65nm SOI CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 460-461, Feb. 2008.
[2] C. Lee and S. I. Liu, “A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 196-197, Feb. 2007. [3] J. Lee and B. Razavi, “A 40-GHz Frequency Divider In 0.18-μm CMOS Technology,” IEEE J. of Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004. [4] H. R. Rategh and T. H. Lee, “Superharmonic Injection-Locked Frequency Dividers,” IEEE J. of Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Jun. 1999. [5] M. Tiebout, “A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency Low-Power Frequency Divider,” IEEE J. of Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, Jul. 2004. [6] P. Mayr, C. Weyers, and U. Langmann,“A 90GHz 65nm CMOS Injection-locked Frequency Divider,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 198-199, Feb. 2007. [7] K. H. Tsai, L. C. Cho, J. H. Wu, and S. I. Liu, “3.5mW W-band Frequency Divider With Wide Locking Lange In 90nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 466-467, Feb. 2008. [8] L. C. Cho, K. H. Tsai, C. C. Hung, and S. I. Liu, “93.5~109.4GHz CMOS Injection- locked Frequency Divider With 15.3% Locking Range,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 266-267, Jun. 2008. [9] B. Y. Lin, K. H. Tsai, and S. I. Liu, “A 128.24-to-137.00GHz Injection-locked Frequency Divider In 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 282-283, Feb. 2009. [10] B. Y. Lin and S. I. Liu, “A 132.7-to-143.5GHz Injection-Locked Frequency Divider In 65nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 230-231, Jun. 2009. [11] B. Y. Lin and S. I. Liu, 'Analysis and Design of D-Band Injection-Locked Frequency Dividers,' IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1250-1264, Jun. 2011. [12] B. Y. Lin, I. T. Lee, C. H. Wang, and S. I. Liu, 'A 198.9-to-201.0GHz injection-locked frequency divider in 65nm CMOS,' IEEE Symp. on VLSI Circuits, June 2010, pp. 49-50. [13] I. T. Lee, C. H. Wang, B. Y. Lin, and S. I. Liu, 'A 258.16-259.95 GHz injection-locked frequency divider,' IET Electronics Letters, vol. 46, no. 21, pp. 1438-1439, Oct. 2010. [14] Q. J. Gu, H. Y. Jian, Z. W. Xu, Y. C. Wu, M. C. F. Chang, Y. Baeyens, and Y. K. Chen, 'CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range,' IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, no. 7, pp. 393-397, July 2011. [15] I. T. Lee and S. I. Liu, 'G-Band injection-locked frequency dividers using π-type LC networks,' IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 59, pp. 315-323, Feb. 2012. [16] F. Tzeng, P. Deyi, A. Safarian, and P. Heydari, “Theoretical Analysis of Novel Multi-Order LC Oscillators,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, no. 3, pp. 287-291, Mar. 2007. [17] B. Razavi, “A millimeter-wave circuit technique,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2090–2098, Sep. 2008. [18] S. Verma, H. R. Rategh, and T. H. Lee, “A Unified Model for Injection-Locked Frequency Dividers,” IEEE J. of Solid-State Circuits, vol. 38, no. 6, pp. 1015-1027, Jun. 2003. [19] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection-Locking Scheme for Precision Quadrature Generation,” IEEE J. of Solid-State Circuits, vol. 37, no. 7, pp. 845-851, Jul. 2002. [20] B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J. of Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004. [21] A. Mazzanti, “Analysis and Design of Injection-Locked LC Dividers for Quadrature Generation,” IEEE J. of Solid-State Circuits, vol. 36, no. 9, pp. 1425-1433, Sep. 2004. [22] K. Yamamoto and M. Fujishima, “A 44-uW 3-GHz Injection-Locked Frequency Divider With 2.3-GHz Locking Range,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp. 671-677, Mar. 2005. [23] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, “The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking,” IEEE J. of Solid-State Circuits, vol. 42, no. 9, pp. 1916-1932, Sep. 2007. [24] T. Shibasaki, “20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range,” IEEE J. of Solid-State Circuits, vol. 43, no. 3, pp. 610-618, Mar. 2008. [25] A. Mirzaei, M. E. Heidari, R. Bagheri, A. A. Abidi, “Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers,” IEEE J. of Solid-State Circuits, vol. 43, no. 3, pp. 656-671, Mar. 2008. [26] Q. Gu, Z. Xu, D. Huang, T. LaRocca, N. Wang, W. Hant, and M. F. Chang, “A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases,” IEEE J. of Solid-State Circuits, vol. 43, no. 4, pp. 991-998, Apr. 2008. [27] H. Zheng and H. Luong, “Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-um CMOS Process,” IEEE J. of Solid-State Circuits, vol. 43, no. 10, pp. 2293-2302, Oct. 2008. [28] C. Y. Wu, and C. Y. Yu, “Design and Analysis of a Millimeter-Wave Direct Injection-Locked Frequency Divider With Large Frequency Locking Range,” IEEE Trans. Microwave Theory and Techniques, vol. 55, no. 8, pp. 1649-1658, Aug. 2007. [29] Z. D. Huang, C. Y. Wu, and B. C. Huang, “Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range,” IEEE Trans. Microwave Theory and Techniques, vol. 57, no. 8, pp. 1948-1958, Aug. 2009 [30] I. T. Lee, K. H. Tsai, and S. I. Liu, “A 104~112.8GHz CMOS Injection-Locked Frequency Divider,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 555-559, July 2009. [31] VDI Source Module, [Online]. Avalable: http://vadiodes.com | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15836 | - |
dc.description.abstract | 隨著現代互補式金氧半場效電晶體製程技術的發展與進步,以往必需使用雙極性接面型電晶體來實現的高速電路將可以被互補式金氧半場效電晶體取代。如此驅使了許多毫米波段應用的發展,例如: 點對點的通訊,影像感測器,車用雷達系統,電波相關天文學。上述應用所使用的振盪器或者通道選擇器當中,鎖相迴路將會是一個關鍵的構成元件
為了實現非常高速的鎖相迴路,位於壓控振盪器後的第一級除頻器將是一個關鍵組件。它必須有很高的操作頻率,寬的鎖定範圍和低功率的消耗。然而在設計毫米波電路時,電感,導線和電晶體的寄生電容會減少電路的操作頻率。在追求高操作頻率,低功率消耗和低相位雜訊時,利用電感和電容為振盪器基礎的注入式鎖定除頻器提供了一個不錯的解決方案。為了實現高速的操作,我們在注入式鎖定除頻器中使用了分佈式電感、並且使電路振盪在第二極點。另外,在兩個電感之間加入互感效應,來加強除頻器的起振條件和增加其鎖定範圍。針對以上設計目的,將在考慮互感效應存在的前提下,對分佈式電感架構第二極點的頻率,以及起振條件進行分析。最後,分析互感效應對於鎖定範圍的影響。同樣的分析方法將被套用在五個不同架構的除頻器上。這五個除頻器使用40奈米的互補式金氧半場效電晶體製程,其中一個注入鎖定頻率最高可達298.7GHz,功率消耗為11.7mW,晶片面積為0.51x0.325mm2。 | zh_TW |
dc.description.abstract | With the development and progress of CMOS process, the high-speed circuits should be realized by BJT in the past are gradually replaced by CMOS. It inspires many millimeter-wave applications; such as point to point communications, image sensing, automotive radar systems, radio astronomy. In above applications, the phase-locked loop (PLL) is an important component to sever as a local oscillator or channel selector.
To realize a very-high-speed PLL, the frequency divider following the voltage-controlled oscillator will be a crucial building block. It must have high operation frequency, wide locking range, and low power consumption. In millimeter wave circuits design, the parasitic capacitances of passive inductors, wire lines and transistors will decrease the operation frequency of circuits. Injection-locked frequency dividers (ILFDs) with LC tank based oscillators can be a good solution for high operation frequency, low power consumption and low phase noise. To achieve high speed, the distributed-LC technique is used and the circuit oscillates at its second pole. In addition, coupled inductors are added to the distributed-LC network to enhance the oscillation condition and increase the locking range. According to above design issues, the operation frequency and oscillation condition of the distributed-LC ILFDs will be analyzed at the second pole with coupled inductors. The relationship of locking range and the coupling factor is also presented. Based on the analysis, five proposed H-band (220-325GHz) divide-by-2 ILFD are fabricated in 40nm CMOS process. One of the ILFDs has the highest injection-locked frequency of 298.7GHz, consumes 11.7mW from a 0.9V power supply; the chip area is 0.51 0.321mm2. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T17:53:14Z (GMT). No. of bitstreams: 1 ntu-101-R98943009-1.pdf: 5169615 bytes, checksum: 01e3fb3667b43a389365faff613bac67 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 摘要 i
Abstract iii Content v List of Figures vii List of Table xi Chapter 1 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 4 2.1 Introduction 4 2.2 ILFD Design 5 2.2.1 Oscillation Frequency 5 2.2.2 Oscillation Condition 9 2.3 Locking Range Analysis 22 2.3.1 The 1st and 2nd divider 23 2.3.2 The 3rd , 4th and 5th dividers 31 2.4 Experimental Results 39 2.4.1 Measurement Setup 39 2.4.2 The 1st divider 41 2.4.3 The 2nd divider 45 2.4.4 The 3rd divider 49 2.4.5 The 4th divider 52 2.4.5 The 5th divider 56 2.5 Summary 59 Chapter 3 61 3.1 Conclusion 61 3.2 Future Work 61 Bibliography 63 | |
dc.language.iso | en | |
dc.title | 應用於H-Band 之注入鎖定除頻器 | zh_TW |
dc.title | H-Band Injection-Locked Frequency Dividers | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 注入鎖定式除頻器,ILFD,毫米波,互感電感,H頻段, | zh_TW |
dc.subject.keyword | Frequency dividers,ILFD,milimeter-wave,coupled inductors,H-band, | en |
dc.relation.page | 66 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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