請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15744
標題: | 四階脈衝振幅調變光接收器前端電路之分析及設計 Design and Analysis of PAM-4 Optical Receiver Front-Ends |
作者: | Kuan-Lin Fu 傅冠霖 |
指導教授: | 劉深淵(Shen-Iuan Liu) |
關鍵字: | 四階脈衝調變(PAM-4),轉阻放大器(TIA),可變增益放大器(VGA),恆定增益放大器(CGA),自動增益控制(AGC),決策回授等化器(DFE),閾值電壓/ 資料位準校準,Sign-Sign最小均方(SSLMS),非等間距(non-equally-spaced), four level pulse amplitude modulation (PAM-4),transimpedance amplifier (TIA),variable gain amplifier (VGA),constant gain amplifier (CGA),automatic gain control (AGC),decision feedback equalizer (DFE),threshold voltage/data level calibration,least-mean square (SSLMS),non-equally-spaced, |
出版年 : | 2020 |
學位: | 博士 |
摘要: | 超高速雲端數據中心與高性能計算運用的頻寬需求增加,需要更高速的光/電輸入與輸出資料。下一個世代400Gbps乙太網路的開發,主要將由8條超過50Gbps傳輸的資料通道所組成,每一條提供至少50Gbps的不歸零信號(non-return-zero, NRZ)或四階脈衝調變(four-level pulse amplitude modulation, PAM-4)的信號。雖然四階脈衝調變的信號比不歸零信號有更好的頻譜效率,但是四階脈衝調變的信號振幅大小縮小三分之一,使訊號雜訊比(signal-to-noise ratio, SNR)降低了9.5 dB,這使PAM-4電路設計非常具有挑戰性。 本論文研究主題可分為兩部分。第一部分,使用40奈米技術下,實現一個56Gbps光前端接收器。為了保持光前端接收器的線性度,使用具有自動增益控制的可變增益放大器。分析五級可變增益放大器與單級可變增益放大器加上四級恆定增益放大器的差異。第二部分,使用40奈米技術下,實現一個64Gbps光接收器具有振幅與相位校正和閾值電壓(Threshold voltage)/資料位準(Data level)校準。在光接收器前端,量測的最大振幅不平衡小於0.4dB,相位不平衡小於±1.0度。理論上,最佳化的訊號雜訊比,PAM-4資料為等間距傳輸。實際上,因為光元件與電路的非理想效應,PAM-4資料為非等間距傳輸。為了考慮非等間距的PAM-4資料,分別調整比較器的閾值電壓。使用3-tap決策回授等化器(Decision feedback equalizer, DFE)。Tap係數和資料位準通過使用Sign-Sign最小均方(Sign-Sign least-mean square, SSLMS)算法進行校準。 Supporting increased bandwidth demand in ultra-high-speed cloud data centers and high-performance computing application requires higher per-lane optical/ electrical I/O data rate. The next generation of 400Gbps Ethernet development is composed of 8 data channels, and each of them delivers at least 50Gbps in data format of non-return-zero (NRZ) or four-level pulse amplitude modulation (PAM-4). Although PAM-4 signal has better spectral efficiency than NRZ signal, the signal swing of PAM-4 shrinking from one to one-third degrades the signal-to-noise ratio (SNR) by 9.5 dB, which makes the circuit of PAM-4 design very challenging. In this dissertation, there are mainly two parts. The first part, a 56Gbps PAM-4 optical receiver front-end is realized in a 40nm CMOS technology. In order to maintain linearity of optical receiver front-end at PAM-4 format, the variable gain amplifier (VGA) with the automatic gain control (AGC) is presented. The noise difference between five stage VGAs, and one stage VGA + four stage constant gain amplifier (CGA) is analyzed. The second part, a 64Gbps PAM-4 optical receiver with amplitude/phase correction and threshold voltage/data level calibration is realized in a 40nm CMOS technology. For the optical receiver front-end, the measured maximum amplitude imbalance is less than 0.4 dB and phase imbalance is less than ±1.0 degree. Theoretically, with the optimized signal-to-noise ratio, PAM-4 data is transmitted at equally-spaced. In fact, because of the non-ideal effects of optical components and electronic circuits, PAM-4 data is transmitted at non-equally-spaced. To consider the non-equally-spaced PAM-4 data, the threshold voltages of the comparators are individually adjusted. A 3-tap decision feedback equalizer (DFE) is used. The tap coefficients and the data levels are calibrated by using the sign-sign least-mean square (SSLMS) algorithm. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15744 |
DOI: | 10.6342/NTU202002244 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
U0001-0308202001203200.pdf 目前未授權公開取用 | 3.06 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。